EPM7128AETC144-10N - MAX 7000A CPLD, 128 Macros, 144-TQFP | Intel
MPN: EPM7128AETC144-10N ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $37.6 | $37.60 |
| 10 | $33.84 | $338.40 |
| 100 | $30.08 | $3,008.00 |
| 500 | $26.32 | $13,160.00 |
| 1,000 | $22.56 | $22,560.00 |
EPM7128AETC144-10N Overview
A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines the instant-on behavior of PAL/GAL architectures with the density and macro-cell richness of small FPGAs. CPLDs sit in the programmable-logic hierarchy above simple PLDs and below FPGAs, and are commonly used for glue logic, bus decoding, address decoding, state-machine control, and power-sequencing tasks in digital systems. The MAX 7000A family uses a classic EE (Electrically Erasable) configuration memory, allowing the device to retain its programmed logic across power cycles without an external configuration PROM.
Key features of the EPM7128AETC144-10N include up to 100 user I/O pins across 4 I/O banks, 128 macro cells, 250 MHz internal performance, JTAG-compliant IEEE 1149.1 boundary-scan support, multiVolt I/O supporting 2.5 V/3.3 V/5 V mixed-voltage interfacing, and a propagation delay of 4.5 ns through the logic array. The device includes a built-in 4-pin JTAG interface (TCK, TMS, TDI, TDO) for in-system programming and boundary-scan testing, eliminating the need for a stand-alone programmer. The 144-pin TQFP package offers a compact surface-mount footprint suitable for production PCB assembly.
Typical applications include bus-interface bridging, peripheral controllers in embedded designs, address decoding for microprocessor and DSP systems, glue logic in industrial control, and state-machine implementation in telecommunications equipment. The part remains in production and is broadly second-sourced through the authorized distributor channel, making it a reliable choice for both legacy maintenance and new designs.
Drop-in alternatives for EPM7128AETC144-10N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EPM7128AETC144-10N (same form factor and footprint) — differing in Operating Temperature, Package, Family, Propagation Delay (tPD), RoHS Status.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPM7128AETC144-7N
✅ Drop-In✓ In Stock
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View Datasheet →EPM7128AETI144-10N
✅ Drop-In✓ In Stock
$23.1 / Unit
View Datasheet →EPM7128AETI144-7N
✅ Drop-In📋 Reference alternative (not in catalog)
EPM7128ATC144-10
✅ Drop-In✓ In Stock
$9.1 / Unit
View Datasheet →EPM7128AEFC144-10
✅ Drop-In📋 Reference alternative (not in catalog)
EPM7128AETC144-10
✅ Drop-In✓ In Stock
$21.7 / Unit
View Datasheet →EPM7128AETC144-10N Maximum Ratings & Electrical Characteristics
| Family | MAX 7000A |
| Number of Macros | 128 |
| Logic Gates | 2,500 usable gates |
| Number of I/O Pins | 100 (max user I/O) |
| Propagation Delay (tPD) | 10 ns (grade -10) |
| Internal Frequency | Up to 250 MHz |
| Supply Voltage (VCCINT) | 3.3 V |
| I/O Standards | 2.5 V / 3.3 V / 5 V multiVolt |
| Configuration Memory | CMOS EEPROM (non-volatile) |
| JTAG Support | IEEE 1149.1 compliant boundary-scan |
| Package | 144-pin TQFP (T144) |
| Mounting Type | Surface Mount |
| Operating Temperature | 0 C to +70 C (commercial) |
EPM7128AETC144-10N Pin Configuration
| Pin 1 | I/O — User I/O (Bank 1) |
| Pin 2 | I/O — User I/O (Bank 1) |
| Pin 3 | I/O — User I/O (Bank 1) |
| Pin 4 | I/O — User I/O (Bank 1) |
| Pin 5 | I/O — User I/O (Bank 1) |
| Pin 6 | I/O — User I/O (Bank 1) |
| Pin 7 | I/O — User I/O (Bank 1) |
| Pin 8 | I/O — User I/O (Bank 1) |
| Pin 9 | GND — Ground |
| Pin 10 | I/O — User I/O (Bank 1) |
| Pin 11 | I/O — User I/O (Bank 1) |
| Pin 12 | I/O — User I/O (Bank 1) |
| Pin 13 | I/O — User I/O (Bank 1) |
| Pin 14 | I/O — User I/O (Bank 1) |
| Pin 15 | I/O — User I/O (Bank 1) |
| Pin 16 | I/O — User I/O (Bank 1) |
| Pin 17 | I/O — User I/O (Bank 1) |
| Pin 18 | I/O — User I/O (Bank 1) |
| Pin 19 | I/O — User I/O (Bank 1) |
| Pin 20 | I/O — User I/O (Bank 1) |
| Pin 21 | I/O — User I/O (Bank 1) |
| Pin 22 | GND — Ground |
| Pin 23 | I/O — User I/O (Bank 1) |
| Pin 24 | I/O — User I/O (Bank 1) |
| Pin 25 | I/O — User I/O (Bank 1) |
| Pin 26 | I/O — User I/O (Bank 1) |
| Pin 27 | I/O — User I/O (Bank 1) |
| Pin 28 | I/O — User I/O (Bank 1) |
| Pin 29 | I/O — User I/O (Bank 2) |
| Pin 30 | VCCINT — Core supply voltage (3.3 V) |
| Pin 31 | I/O — User I/O (Bank 2) |
| Pin 32 | I/O — User I/O (Bank 2) |
| Pin 33 | I/O — User I/O (Bank 2) |
| Pin 34 | I/O — User I/O (Bank 2) |
| Pin 35 | GND — Ground |
| Pin 36 | I/O — User I/O (Bank 2) |
| Pin 37 | I/O — User I/O (Bank 2) |
| Pin 38 | I/O — User I/O (Bank 2) |
| Pin 39 | I/O — User I/O (Bank 2) |
| Pin 40 | I/O — User I/O (Bank 2) |
| Pin 41 | I/O — User I/O (Bank 2) |
| Pin 42 | VCCIO2 — I/O supply voltage Bank 2 |
| Pin 43 | I/O — User I/O (Bank 2) |
| Pin 44 | I/O — User I/O (Bank 2) |
| Pin 45 | I/O — User I/O (Bank 2) |
| Pin 46 | I/O — User I/O (Bank 2) |
| Pin 47 | I/O — User I/O (Bank 2) |
| Pin 48 | I/O — User I/O (Bank 2) |
| Pin 49 | GND — Ground |
| Pin 50 | I/O — User I/O (Bank 2) |
| Pin 51 | I/O — User I/O (Bank 2) |
| Pin 52 | I/O — User I/O (Bank 2) |
| Pin 53 | I/O — User I/O (Bank 2) |
| Pin 54 | I/O — User I/O (Bank 2) |
| Pin 55 | I/O — User I/O (Bank 2) |
| Pin 56 | I/O — User I/O (Bank 2) |
| Pin 57 | TDI — JTAG Test Data In |
| Pin 58 | TMS — JTAG Test Mode Select |
| Pin 59 | TCK — JTAG Test Clock |
| Pin 60 | GND — Ground |
| Pin 61 | TDO — JTAG Test Data Out |
| Pin 62 | I/O — User I/O (Bank 3) |
| Pin 63 | I/O — User I/O (Bank 3) |
| Pin 64 | I/O — User I/O (Bank 3) |
| Pin 65 | I/O — User I/O (Bank 3) |
| Pin 66 | I/O — User I/O (Bank 3) |
| Pin 67 | I/O — User I/O (Bank 3) |
| Pin 68 | I/O — User I/O (Bank 3) |
| Pin 69 | I/O — User I/O (Bank 3) |
| Pin 70 | GND — Ground |
| Pin 71 | VCCIO3 — I/O supply voltage Bank 3 |
| Pin 72 | I/O — User I/O (Bank 3) |
| Pin 73 | I/O — User I/O (Bank 3) |
| Pin 74 | I/O — User I/O (Bank 3) |
| Pin 75 | I/O — User I/O (Bank 3) |
| Pin 76 | I/O — User I/O (Bank 3) |
| Pin 77 | I/O — User I/O (Bank 3) |
| Pin 78 | I/O — User I/O (Bank 3) |
| Pin 79 | I/O — User I/O (Bank 3) |
| Pin 80 | I/O — User I/O (Bank 3) |
| Pin 81 | I/O — User I/O (Bank 3) |
| Pin 82 | GND — Ground |
| Pin 83 | I/O — User I/O (Bank 3) |
| Pin 84 | I/O — User I/O (Bank 3) |
| Pin 85 | I/O — User I/O (Bank 3) |
| Pin 86 | I/O — User I/O (Bank 3) |
| Pin 87 | I/O — User I/O (Bank 3) |
| Pin 88 | I/O — User I/O (Bank 3) |
| Pin 89 | I/O — User I/O (Bank 4) |
| Pin 90 | I/O — User I/O (Bank 4) |
| Pin 91 | I/O — User I/O (Bank 4) |
| Pin 92 | I/O — User I/O (Bank 4) |
| Pin 93 | GND — Ground |
| Pin 94 | I/O — User I/O (Bank 4) |
| Pin 95 | I/O — User I/O (Bank 4) |
| Pin 96 | I/O — User I/O (Bank 4) |
| Pin 97 | I/O — User I/O (Bank 4) |
| Pin 98 | I/O — User I/O (Bank 4) |
| Pin 99 | I/O — User I/O (Bank 4) |
| Pin 100 | VCCIO4 — I/O supply voltage Bank 4 |
| Pin 101 | I/O — User I/O (Bank 4) |
| Pin 102 | I/O — User I/O (Bank 4) |
| Pin 103 | I/O — User I/O (Bank 4) |
| Pin 104 | I/O — User I/O (Bank 4) |
| Pin 105 | I/O — User I/O (Bank 4) |
| Pin 106 | I/O — User I/O (Bank 4) |
| Pin 107 | GND — Ground |
| Pin 108 | I/O — User I/O (Bank 4) |
| Pin 109 | I/O — User I/O (Bank 4) |
| Pin 110 | I/O — User I/O (Bank 4) |
| Pin 111 | I/O — User I/O (Bank 4) |
| Pin 112 | I/O — User I/O (Bank 4) |
| Pin 113 | I/O — User I/O (Bank 4) |
| Pin 114 | I/O — User I/O (Bank 4) |
| Pin 115 | I/O — User I/O (Bank 4) |
| Pin 116 | I/O — User I/O (Bank 4) |
| Pin 117 | I/O — User I/O (Bank 4) |
| Pin 118 | GND — Ground |
| Pin 119 | I/O — User I/O (Bank 4) |
| Pin 120 | I/O — User I/O (Bank 4) |
| Pin 121 | I/O — User I/O (Bank 4) |
| Pin 122 | I/O — User I/O (Bank 1) |
| Pin 123 | I/O — User I/O (Bank 1) |
| Pin 124 | I/O — User I/O (Bank 1) |
| Pin 125 | I/O — User I/O (Bank 1) |
| Pin 126 | VCCINT — Core supply voltage (3.3 V) |
| Pin 127 | I/O — User I/O (Bank 1) |
| Pin 128 | I/O — User I/O (Bank 1) |
| Pin 129 | GND — Ground |
| Pin 130 | I/O — User I/O (Bank 1) |
| Pin 131 | I/O — User I/O (Bank 1) |
| Pin 132 | I/O — User I/O (Bank 1) |
| Pin 133 | I/O — User I/O (Bank 1) |
| Pin 134 | I/O — User I/O (Bank 1) |
| Pin 135 | I/O — User I/O (Bank 1) |
| Pin 136 | I/O — User I/O (Bank 1) |
| Pin 137 | I/O — User I/O (Bank 1) |
| Pin 138 | I/O — User I/O (Bank 1) |
| Pin 139 | I/O — User I/O (Bank 1) |
| Pin 140 | I/O — User I/O (Bank 1) |
| Pin 141 | I/O — User I/O (Bank 1) |
| Pin 142 | I/O — User I/O (Bank 1) |
| Pin 143 | I/O — User I/O (Bank 1) |
| Pin 144 | GND — Ground |
Typical Applications
EPM7128AETC144-10N is suitable for 7 applications: Bus Address Decoding, Peripheral Glue Logic, State Machine Controllers, Level Translation Bridges, Power Sequencing Controllers, Telecom Line-Card Logic, Industrial Control Glue Logic.
Bus Address Decoding
The EPM7128AETC144-10N delivers deterministic 10 ns pin-to-pin decoding across 100 user I/Os, making it ideal for address decoding in microprocessor and DSP systems. With 128 macro cells it can decode wide address ranges, generate chip-selects, and remap memory regions without external decoder ICs. The non-volatile EEPROM configuration retains decode logic across power cycles for instant-on behavior, eliminating boot-PROM access latency at reset. MultiVolt I/O supports 5 V/3.3 V mixed-voltage buses, allowing direct interface to legacy 5 V peripherals alongside modern 3.3 V processors on the same board.
Recommended
Peripheral Glue Logic
The EPM7128AETC144-10N replaces dozens of 74xx discrete logic gates with a single programmable device, simplifying board layout and reducing BOM cost. Its 128 macro cells and 4.5 ns internal propagation handle combinational gating, latching, and pulse generation for interfacing peripherals such as UARTs, FIFOs, and display controllers to a host CPU. The 100 user I/Os accommodate wide data buses plus control signals without multiplexing, while JTAG support enables in-system reprogramming for late-stage logic changes without board rework.
Recommended
State Machine Controllers
The EPM7128AETC144-10N's predictable 10 ns timing and 16 macro-cell logic array blocks (LABs) make it well suited for implementing complex state machines in industrial control, motor control, and instrumentation front-ends. Up to 250 MHz internal performance supports high-speed sequencing, while EEPROM non-volatile storage ensures the state machine retains its firmware across power cycles. JTAG in-system programming allows field upgrades of state-machine definitions without removing the part from the PCB.
Recommended
Level Translation Bridges
The EPM7128AETC144-10N's multiVolt I/O supports direct interfacing between 5 V, 3.3 V, and 2.5 V logic domains in mixed-voltage systems. Its 100 user I/Os allow many translation channels in a single chip, replacing discrete level-shifters. With 10 ns propagation the bridge adds minimal latency, important for memory buses and high-speed peripheral interfaces. Commercial temperature range (0 C to +70 C) suits indoor industrial and consumer applications.
Recommended
Power Sequencing Controllers
The EPM7128AETC144-10N is widely used in board-level power sequencing, generating timed enable signals for multiple voltage rails in storage controllers, networking line cards, and ATCA-style backplanes. Its deterministic 10 ns timing ensures precise rail-on delays, while 100 user I/Os can monitor PG (power-good) feedback and drive dozens of load-switch enables simultaneously. The EEPROM-backed logic retains sequencing order across power cycles with no boot firmware dependency.
Recommended
Telecom Line-Card Logic
In telecom line cards the EPM7128AETC144-10N provides bus arbitration, interrupt aggregation, and timing-strobe generation between framers, mappers, and switch fabrics. Its 128 macro cells handle complex multi-channel logic while the JTAG boundary-scan supports board-level testability required by carrier-class reliability standards. The 144-pin TQFP provides 100 user I/Os to interface with parallel telecom buses and control EEPROMs without multiplexing.
Recommended
Industrial Control Glue Logic
In PLCs and industrial I/O modules the EPM7128AETC144-10N provides deterministic glue logic for optocoupler interfaces, watchdog timers, and safe-state controllers. With 100 user I/Os it can manage large DIN-rail I/O counts, while its 10 ns propagation enables fast fault-detection response. JTAG in-system programming allows on-site logic updates as control algorithms evolve, reducing service-call cost for installed systems.
Recommended
Recommended Products Summary
Engineering reference data for EPM7128AETC144-10N — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM7128AETC144-7N | EPM7128AETI144-10N | EPM7128AETI144-7N | EPM7128ATC144-10 | EPM7128AEFC144-10 | EPM7128AETC144-10 |
|---|---|---|---|---|---|---|---|
| Package | 144-pin TQFP | 144-pin TQFP - same | 144-pin TQFP - same | 144-pin TQFP - same | 144-pin TQFP - same | 144-pin TQFP - same | 144-pin TQFP - same |
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Family | MAX 7000A | MAX 7000A | MAX 7000A | MAX 7000A | MAX 7000 (legacy) | MAX 7000A | MAX 7000A |
| Macro Cells | 128 | 128 | 128 | 128 | 128 | 128 | 128 |
| Propagation Delay (tPD) | 10 ns | 7 ns (-30%) | 10 ns | 7 ns (-30%) | 10 ns | 10 ns | 10 ns |
| Operating Temperature | 0 C to +70 C (Commercial) | 0 C to +70 C (Commercial) | -40 C to +85 C (Industrial) | -40 C to +85 C (Industrial) | 0 C to +70 C (Commercial) | 0 C to +70 C (Commercial) | 0 C to +70 C (Commercial) |
| Core Voltage (VCCINT) | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 5.0 V | 3.3 V | 3.3 V |
| Internal Frequency | Up to 250 MHz | Up to 250 MHz | Up to 250 MHz | Up to 250 MHz | Up to 200 MHz | Up to 250 MHz | Up to 250 MHz |
Key Differentiators
- MultiVolt I/O supporting 5 V / 3.3 V / 2.5 V mixed-voltage interfacing (vs EPM7128ATC144-10)
- Industry-standard 144-pin TQFP with broad second-source availability (vs EPM7128AEFC144-10 (144-FBGA variant))
- 10 ns speed grade offers balanced cost-performance for general glue logic (vs EPM7128AETC144-7N)
Design Notes
The EPM7128AETC144-10N requires a clean 3.3 V supply on all VCCINT pins and per-bank VCCIO pins. Decouple each VCCINT pin with a 0.1 uF X7R ceramic capacitor placed within 5 mm of the package, plus a bulk 10 uF tantalum or ceramic near the supply via. Programmed-in-advance current is typically under 200 mA during normal operation, but in-system programming (ISP) via JTAG can momentarily increase supply current; ensure regulator headroom accordingly.
Route JTAG signals (TCK, TMS, TDI, TDO) with 50 ohm controlled impedance and keep traces short. The 144-pin TQFP has 0.5 mm pitch; use 4-mil traces with 4-mil spaces and a via-in-pad escape pattern to breakout inner-pin signals cleanly. Provide a solid ground plane on the layer immediately adjacent to the TQFP to control return paths for high-speed signals.
Estimated: at the rated 250 MHz internal frequency, output edge rates of approximately 1-2 ns require source-series termination (22-33 ohm) on outputs driving long traces (>50 mm) or backplane connectors. Group multiVolt I/O banks carefully - mixing 5 V and 3.3 V logic on the same bank violates the multiVolt specification and risks device damage.
Do not leave JTAG pins floating during operation - tie TMS and TDI high through 10 kohm pull-ups and TCK low through 10 kohm to prevent spurious configuration events. Always connect all GND pins (multiple GND pins exist for thermal and signal return) - unused GND pins must still be soldered for thermal dissipation and signal-integrity reasons.
Compliance Information
Specific RoHS/REACH compliance status was not available in the verified web data. As an Intel/Altera product sold in 2026 through authorized distributors, RoHS compliance is expected for the 'N' suffix variant (Pb-free).
