EPM7128AETC144-10 - 128-Macrocell MAX 7000A CPLD, 10ns TQFP-144
MPN: EPM7128AETC144-10 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $36.17 | $36.17 |
| 10 | $32.55 | $325.50 |
| 100 | $28.93 | $2,893.00 |
| 500 | $25.32 | $12,660.00 |
| 1,000 | $21.7 | $21,700.00 |
Drop-in alternatives for EPM7128AETC144-10 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM7128AETC144-10N
β Drop-Inπ Reference alternative (not in catalog)
EPM7128AETC144-7
β Drop-Inβ In Stock
$16.4 / Unit
View Datasheet βEPM7128AETC144-15
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
EPM7128AETI144-7
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
EPM7128AETC144-10 Maximum Ratings & Electrical Characteristics
| Family | MAX 7000A |
| Macrocells | 128 |
| Usable Gates | 2,500 |
| Logic Array Blocks (LABs) | 8 |
| Maximum User I/Os | 36 |
| Pin-to-pin Logic Delay (tPD) | 10 ns |
| Maximum Internal Counter Frequency | 98 MHz |
| Supply Voltage (Core) | 3.3 V |
| I/O Voltage Tolerance | 2.5 V / 3.3 V / 5 V |
| Operating Temperature | 0C to +70C (Commercial) |
| Package | 144-pin TQFP (also referred to as LQFP-144) |
| Programming Interface | JTAG (IEEE Std. 1149.1) and ByteBlaster |
| Non-volatile Memory | EEPROM, instant-on |
| Global Clocks / Global OE | 2 / 2 |
| Mounting Type | Surface Mount |
| MSL Level | MSL 3 (per JEDEC J-STD-020) |
EPM7128AETC144-10 Pin Configuration
| Pin 1 | OE1 β Global output enable 1 (active low) |
| Pin 2 | GCLRn β Global clear (active low) |
| Pin 3 | I/O β User I/O pin (bank 1) |
| Pin 4 | I/O β User I/O pin (bank 1) |
| Pin 5 | I/O β User I/O pin (bank 1) |
| Pin 6 | I/O β User I/O pin (bank 1) |
| Pin 7 | I/O β User I/O pin (bank 1) |
| Pin 8 | I/O β User I/O pin (bank 1) |
| Pin 9 | GND β Ground |
| Pin 10 | I/O β User I/O pin (bank 1) |
| Pin 11 | I/O β User I/O pin (bank 1) |
| Pin 12 | I/O β User I/O pin (bank 1) |
| Pin 13 | I/O β User I/O pin (bank 1) |
| Pin 14 | I/O β User I/O pin (bank 1) |
| Pin 15 | I/O β User I/O pin (bank 1) |
| Pin 16 | GND β Ground |
| Pin 17 | I/O β User I/O pin (bank 2) |
| Pin 18 | I/O β User I/O pin (bank 2) |
| Pin 19 | I/O β User I/O pin (bank 2) |
| Pin 20 | I/O β User I/O pin (bank 2) |
| Pin 21 | I/O β User I/O pin (bank 2) |
| Pin 22 | I/O β User I/O pin (bank 2) |
| Pin 23 | GND β Ground |
| Pin 24 | I/O β User I/O pin (bank 2) |
| Pin 25 | I/O β User I/O pin (bank 2) |
| Pin 26 | I/O β User I/O pin (bank 2) |
| Pin 27 | I/O β User I/O pin (bank 2) |
| Pin 28 | I/O β User I/O pin (bank 2) |
| Pin 29 | I/O β User I/O pin (bank 2) |
| Pin 30 | GND β Ground |
| Pin 31 | I/O β User I/O pin (bank 2) |
| Pin 32 | I/O β User I/O pin (bank 2) |
| Pin 33 | I/O β User I/O pin (bank 2) |
| Pin 34 | I/O β User I/O pin (bank 2) |
| Pin 35 | I/O β User I/O pin (bank 2) |
| Pin 36 | I/O β User I/O pin (bank 2) |
| Pin 37 | GND β Ground |
| Pin 38 | I/O β User I/O pin (bank 3) |
| Pin 39 | I/O β User I/O pin (bank 3) |
| Pin 40 | I/O β User I/O pin (bank 3) |
| Pin 41 | I/O β User I/O pin (bank 3) |
| Pin 42 | I/O β User I/O pin (bank 3) |
| Pin 43 | GCLK1 β Global clock input 1 |
| Pin 44 | GCLK2 β Global clock input 2 |
| Pin 45 | I/O β User I/O pin (bank 3) |
| Pin 46 | I/O β User I/O pin (bank 3) |
| Pin 47 | I/O β User I/O pin (bank 3) |
| Pin 48 | I/O β User I/O pin (bank 3) |
| Pin 49 | I/O β User I/O pin (bank 3) |
| Pin 50 | I/O β User I/O pin (bank 3) |
| Pin 51 | I/O β User I/O pin (bank 3) |
| Pin 52 | GND β Ground |
| Pin 53 | I/O β User I/O pin (bank 3) |
| Pin 54 | I/O β User I/O pin (bank 3) |
| Pin 55 | I/O β User I/O pin (bank 3) |
| Pin 56 | I/O β User I/O pin (bank 3) |
| Pin 57 | I/O β User I/O pin (bank 3) |
| Pin 58 | I/O β User I/O pin (bank 3) |
| Pin 59 | GND β Ground |
| Pin 60 | I/O β User I/O pin (bank 4) |
| Pin 61 | I/O β User I/O pin (bank 4) |
| Pin 62 | I/O β User I/O pin (bank 4) |
| Pin 63 | I/O β User I/O pin (bank 4) |
| Pin 64 | I/O β User I/O pin (bank 4) |
| Pin 65 | I/O β User I/O pin (bank 4) |
| Pin 66 | I/O β User I/O pin (bank 4) |
| Pin 67 | I/O β User I/O pin (bank 4) |
| Pin 68 | I/O β User I/O pin (bank 4) |
| Pin 69 | GND β Ground |
| Pin 70 | I/O β User I/O pin (bank 4) |
| Pin 71 | I/O β User I/O pin (bank 4) |
| Pin 72 | I/O β User I/O pin (bank 4) |
| Pin 73 | I/O β User I/O pin (bank 4) |
| Pin 74 | I/O β User I/O pin (bank 4) |
| Pin 75 | I/O β User I/O pin (bank 4) |
| Pin 76 | GND β Ground |
| Pin 77 | I/O β User I/O pin (bank 5) |
| Pin 78 | I/O β User I/O pin (bank 5) |
| Pin 79 | I/O β User I/O pin (bank 5) |
| Pin 80 | I/O β User I/O pin (bank 5) |
| Pin 81 | I/O β User I/O pin (bank 5) |
| Pin 82 | I/O β User I/O pin (bank 5) |
| Pin 83 | I/O β User I/O pin (bank 5) |
| Pin 84 | GND β Ground |
| Pin 85 | I/O β User I/O pin (bank 5) |
| Pin 86 | I/O β User I/O pin (bank 5) |
| Pin 87 | I/O β User I/O pin (bank 5) |
| Pin 88 | I/O β User I/O pin (bank 5) |
| Pin 89 | I/O β User I/O pin (bank 5) |
| Pin 90 | I/O β User I/O pin (bank 5) |
| Pin 91 | I/O β User I/O pin (bank 5) |
| Pin 92 | GND β Ground |
| Pin 93 | I/O β User I/O pin (bank 6) |
| Pin 94 | I/O β User I/O pin (bank 6) |
| Pin 95 | I/O β User I/O pin (bank 6) |
| Pin 96 | I/O β User I/O pin (bank 6) |
| Pin 97 | I/O β User I/O pin (bank 6) |
| Pin 98 | I/O β User I/O pin (bank 6) |
| Pin 99 | I/O β User I/O pin (bank 6) |
| Pin 100 | I/O β User I/O pin (bank 6) |
| Pin 101 | GND β Ground |
| Pin 102 | I/O β User I/O pin (bank 6) |
| Pin 103 | I/O β User I/O pin (bank 6) |
| Pin 104 | I/O β User I/O pin (bank 6) |
| Pin 105 | I/O β User I/O pin (bank 6) |
| Pin 106 | I/O β User I/O pin (bank 6) |
| Pin 107 | I/O β User I/O pin (bank 6) |
| Pin 108 | GND β Ground |
| Pin 109 | I/O β User I/O pin (bank 7) |
| Pin 110 | I/O β User I/O pin (bank 7) |
| Pin 111 | I/O β User I/O pin (bank 7) |
| Pin 112 | I/O β User I/O pin (bank 7) |
| Pin 113 | I/O β User I/O pin (bank 7) |
| Pin 114 | I/O β User I/O pin (bank 7) |
| Pin 115 | I/O β User I/O pin (bank 7) |
| Pin 116 | I/O β User I/O pin (bank 7) |
| Pin 117 | GND β Ground |
| Pin 118 | I/O β User I/O pin (bank 7) |
| Pin 119 | I/O β User I/O pin (bank 7) |
| Pin 120 | I/O β User I/O pin (bank 7) |
| Pin 121 | I/O β User I/O pin (bank 7) |
| Pin 122 | I/O β User I/O pin (bank 7) |
| Pin 123 | I/O β User I/O pin (bank 7) |
| Pin 124 | I/O β User I/O pin (bank 7) |
| Pin 125 | GND β Ground |
| Pin 126 | I/O β User I/O pin (bank 8) |
| Pin 127 | I/O β User I/O pin (bank 8) |
| Pin 128 | I/O β User I/O pin (bank 8) |
| Pin 129 | I/O β User I/O pin (bank 8) |
| Pin 130 | I/O β User I/O pin (bank 8) |
| Pin 131 | I/O β User I/O pin (bank 8) |
| Pin 132 | I/O β User I/O pin (bank 8) |
| Pin 133 | I/O β User I/O pin (bank 8) |
| Pin 134 | GND β Ground |
| Pin 135 | I/O β User I/O pin (bank 8) |
| Pin 136 | I/O β User I/O pin (bank 8) |
| Pin 137 | I/O β User I/O pin (bank 8) |
| Pin 138 | I/O β User I/O pin (bank 8) |
| Pin 139 | I/O β User I/O pin (bank 8) |
| Pin 140 | I/O β User I/O pin (bank 8) |
| Pin 141 | I/O β User I/O pin (bank 8) |
| Pin 142 | OE2 β Global output enable 2 (active low) |
| Pin 143 | VCC β 3.3V core supply |
| Pin 144 | VCCIO β I/O supply (2.5V/3.3V/5V tolerant) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM7128AETC144-10 is suitable for 7 applications: Bus Interface Bridging and Address Decoding, Industrial Control State Machines, Legacy Telecom Line Card Glue Logic, Peripheral I/O Expansion and GPIO Multiplexing, Military and Avionics Retrofit (Legacy), Test and Measurement Front-End Logic, Display Controller Interfacing.
Bus Interface Bridging and Address Decoding
The EPM7128AETC144-10 excels at bus-interface bridging in legacy industrial backplanes where a 3.3V/5V-tolerant CPLD must decode addresses, generate chip selects, and arbitrate interrupts across a 16- or 32-bit bus. Its 128 macrocells and 36 user I/Os comfortably absorb full 8-bit chip-select decoders with one-hot or binary encoding, plus wait-state insertion logic, while the 10 ns tPD guarantees sub-bus-clock timing closure. Designers typically wire OE1 and OE2 as global output enables tied to read/write strobes, and use GCLK1/GCLK2 for synchronous handshake logic. Unlike an FPGA, the EEPROM-based MAX 7000A boots in microseconds with no external PROM, making the part ideal for cold-start deterministic systems.
Recommended
Industrial Control State Machines
The EPM7128AETC144-10 is widely deployed in PLC and motor-control boards implementing deterministic state machines for valve sequencing, conveyor indexing, and safety interlocks. The 128 macrocells comfortably encode 8- to 16-state Moore or Mealy machines with parallel output decoding, while the 10 ns combinatorial delay keeps state transitions well within typical 1 ms scan-cycle budgets. The MAX 7000A EEPROM fabric means the controller boots into a known state at power-on with no configuration flash, a property required by IEC 61508 SIL-1/SIL-2 systems. The commercial 0C to +70C temperature range covers most factory-floor enclosures, and the JTAG interface lets engineers iterate on state tables via Quartus Prime during commissioning.
Recommended
Legacy Telecom Line Card Glue Logic
In T1/E1 and DSLAM line-card designs, the EPM7128AETC144-10 serves as glue logic between framers, LIUs (line interface units), and the central switching ASIC. Its 5V-tolerant I/Os connect directly to legacy bipolar ECL/TTL framers, while the 3.3V core talks to modern CMOS ASICs, eliminating level translators. With 36 user I/Os the device can manage HDLC channel mapping, framer alarm aggregation, and per-port loopback switching on a single chip. The 10 ns tPD ensures that per-port status registers are latched before the next 8 kHz frame pulse. The MAX 7000A's non-volatile configuration also keeps the line card in a safe default state during firmware updates.
Recommended
Peripheral I/O Expansion and GPIO Multiplexing
The EPM7128AETC144-10 is a strong choice for I/O expansion where an SoC lacks sufficient GPIOs for LCD, keypad, and peripheral multiplexing. With 36 user I/Os and 5V tolerance, the device can directly drive character LCDs, scan 4x4 keypads, and arbitrate SPI/I2C/UART buses without external level shifters. The EEPROM fabric lets designers iterate on pin maps during prototype without re-flashing an MCU. The 10 ns combinatorial delay ensures glitch-free mux switching, and the JTAG interface supports boundary-scan (IEEE 1149.1) for board-level interconnect test, dramatically simplifying in-circuit test of dense mixed-signal PCBs.
Recommended
Military and Avionics Retrofit (Legacy)
The EPM7128AETC144-10 remains in long-life avionics retrofit programs where the MAX 7000A is already qualified to DO-254 Design Assurance Level C. Its deterministic 10 ns timing, EEPROM non-volatility, and proven flight heritage make it suitable for cockpit display multiplexing, navigation sensor arbitration, and redundant bus voting. The 144-TQFP package withstands the standard aerospace thermal cycling profile when paired with proper underfill. Note that for new aerospace programs designers should evaluate MAX V or radiation-tolerant FPGAs, as the original 7000A family is NRND and not recommended for new safety-critical designs.
Recommended
Test and Measurement Front-End Logic
In bench-top oscilloscopes, logic analyzers, and protocol testers, the EPM7128AETC144-10 implements front-end channel switching, range relay control, and trigger-arm logic. The 5V-tolerant I/Os drive legacy analog switches directly, while the 3.3V core interfaces to modern ADC front-ends. The 128 macrocells absorb full trigger sequencers with pre-/post-/holdoff counters, and the 10 ns tPD ensures trigger-to-acquisition latency stays below one ADC sample clock. The EEPROM fabric allows trigger logic to be customized per product variant (e.g., UART vs SPI vs I2C triggering) without changing the firmware image.
Recommended
Display Controller Interfacing
The EPM7128AETC144-10 bridges TFT LCD panels to legacy 8/16-bit microcontroller buses by generating WR/RD strobes, converting pixel data timing, and providing backlight PWM control. The 36 user I/Os comfortably handle 16-bit data plus control signals, while the EEPROM fabric stores per-panel timing parameters in logic without external EEPROM. The 10 ns tPD keeps pixel-clock-to-data setup margin healthy even at 25 MHz WVGA timings. The 5V-tolerant I/Os allow direct connection to industrial 5V MCU buses, eliminating level shifters in cost-sensitive HMI designs.
Recommended
Recommended Products Summary
Engineering reference data for EPM7128AETC144-10 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM7128AETC144-10N | EPM7128AETC144-7 | EPM7128AETC144-15 | EPM7128AETI144-7 | EPM7128AETC100-10 |
|---|---|---|---|---|---|---|
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Package | 144-pin TQFP | 144-pin TQFP - same | 144-pin TQFP - same | 144-pin TQFP - same | 144-pin TQFP - same | 100-pin TQFP - different |
| Macrocells | 128 | 128 | 128 | 128 | 128 | 128 |
| Pin-to-pin Delay (tPD) | 10 ns | 10 ns | 7 ns (faster) | 15 ns (slower) | 7 ns (faster) | 10 ns |
| Maximum Internal Frequency | 98 MHz | 98 MHz | 125 MHz | 83 MHz | 125 MHz | 98 MHz |
| Maximum User I/Os | 36 | 36 | 36 | 36 | 36 | 84 (different package) |
| Temperature Grade | Commercial (0C to +70C) | Commercial (0C to +70C) | Commercial (0C to +70C) | Commercial (0C to +70C) | Industrial (-40C to +85C) | Commercial (0C to +70C) |
| Lead-free Plating | Standard (SnPb) | Pb-free (NiPdAu) | Standard (SnPb) | Standard (SnPb) | Standard (SnPb) | Standard (SnPb) |
| Unit Price (USD, qty 1) | 36.17 | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
Key Differentiators
- Drop-in 144-TQFP compatibility with -7 and -15 speed grades (vs EPM7128AETC144-7 / EPM7128AETC144-15)
- Non-volatile EEPROM fabric, instant-on at power-up (vs SRAM-based FPGAs (e.g. Cyclone, Spartan))
- 5V-tolerant I/Os on a 3.3V core (vs Pure 3.3V CPLDs (e.g. MAX II))
Design Notes
Estimated: The MAX 7000A core draws approximately 10 mA quiescent plus dynamic current during toggling; at 100 MHz toggle rate with 36 I/Os switching 5 pF loads, expect 30-50 mA additional. Provide a 100 uF bulk capacitor plus 0.1 uF decoupling within 5 mm of each VCC/VCCIO pin pair. Although the core runs on 3.3V, the I/O banks tolerate 2.5V/3.3V/5V inputs when VCCIO is set accordingly, allowing mixed-voltage buses without level shifters.
The 144-pin TQFP has a 0.5 mm pitch; route signals on the top layer with 0.2 mm trace/space and use a 4-layer stack-up with dedicated ground/power planes. Keep JTAG traces (TCK/TMS/TDI/TDO) short (<50 mm) and series-terminate TCK with 33 ohm to suppress ringing on the 1149.1 boundary-scan clock. Expose all four JTAG signals on a 2x5 header to support ByteBlaster MV programming in-circuit.
Always specify the 'N' suffix (EPM7128AETC144-10N) for new designs to ensure Pb-free / RoHS-compliant assembly per JEDEC J-STD-020 MSL3. Do not confuse the EPM7128AETC144-10 with the EPM7128AETC100-10 (different package, fewer user I/Os even though macrocells match) - they are NOT drop-in compatible. When migrating to MAX II (EPM570), note that the MAX II has a different JTAG chain ordering and requires Quartus Prime re-programming.
For high-speed outputs (>50 MHz toggle), place 22 ohm series resistors near the CPLD pin to dampen transmission-line reflections into the 50 ohm micro-strip. Slew-rate control is available per pin via Quartus Prime (slow slew option) and should be enabled on long board traces to reduce EMI. Global clocks GCLK1/GCLK2 should be driven from a low-skew clock buffer; do not use regular I/O pins for clock distribution above 50 MHz.
Compliance Information
Standard EPM7128AETC144-10 has SnPb lead finish and is RoHS non-compliant; choose the -10N suffix variant for Pb-free RoHS-compliant assembly. The MAX 7000A family is not AEC-Q100 qualified (automotive designers should evaluate automotive-grade CPLDs). REACH compliance confirmed by Intel product declaration.
