EPM7128ATC144-10 - 128-Macrocell MAX 7000A CPLD | Intel / Altera
部品番号: EPM7128ATC144-10 ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $14.5 | $14.50 |
| 10 | $13.2 | $132.00 |
| 100 | $11.85 | $1,185.00 |
| 500 | $10.4 | $5,200.00 |
| 1,000 | $9.1 | $9,100.00 |
EPM7128ATC144-10 概要
A CPLD (Complex Programmable Logic Device) is a non-volatile, flash- or EEPROM-based programmable logic device that combines the instant-on, deterministic timing of PAL/GAL architecture with the density and flexibility of multiple logic blocks interconnected through a programmable switch matrix. Positioned in the programmable logic hierarchy, CPLDs sit between simple SPLDs (PALs/GALs) and high-density FPGAs; they are typically chosen over FPGAs when design size is modest but deterministic propagation delay, multi-voltage I/O compatibility, and in-system programmability (ISP) through the IEEE 1149.1 JTAG interface are required.
Key features include 3.3 V core supply with MultiVolt I/O supporting 5.0 V, 3.3 V, and 2.5 V logic levels, in-system programmability via the built-in JTAG (IEEE Std 1149.1) Joint Test Action Group (JTAG) interface, and on-chip EEPROM configuration memory that eliminates the need for external boot PROMs. The device operates across the commercial 0C to 70C temperature range, is housed in a 144-pin Thin Quad Flat Pack (TQFP) measuring 20 x 20 mm, and offers four user I/O banks for mixed-voltage interfacing.
Architecturally, the MAX 7000A uses a second-generation Multiple Array Matrix (MAX) architecture that combines fine-grained logic elements with a continuous interconnect backbone, providing predictable timing closure independent of design placement. Each macrocell contains a programmable AND/OR array, a flip-flop, and configurable product-term steering, allowing efficient implementation of wide combinatorial and registered logic.
Typical applications include bus-interface bridging (e.g., PCI-to-ISA glue logic), address decoding and wait-state generation in legacy microprocessors, peripheral chip-select generation, LED and LCD scan controllers, and I/O expansion in 5 V/3.3 V mixed-voltage systems. It is also widely used as a pin-compatible replacement for aging discrete TTL/CMOS glue logic.
When designing with this device, ensure that the JTAG chain (TCK, TMS, TDI, TDO) is properly terminated and that unused I/O pins are configured as outputs or tri-stated per datasheet recommendations to minimize supply noise. ByteBlaster or USB-Blaster download cables are supported for ISP through the JTAG pins. The 144-pin TQFP footprint is shared across the MAX 7000A family, simplifying migration to higher- or lower-density siblings such as EPM7064A or EPM7256A.
ドロップイン代替品: EPM7128ATC144-10 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EPM7128ATC144-10 （同一形状・フットプリント） — 相違点: Package, Supply Voltage (VCCINT), Operating Temperature, Configuration Memory, Process Technology.
クイック比較ツール — 並列比較する代替部品を選択:
EPM7128AETC144-10
✅ ドロップイン✓ 在庫あり
$21.7 / 個
データシートを見る →EPM7128AETC144-7N
✅ ドロップイン✓ 在庫あり
$39.82 / 個
データシートを見る →EPM7128AETC144-7
✅ ドロップイン✓ 在庫あり
$16.4 / 個
データシートを見る →EPM7128AETI144-10N
✅ ドロップイン✓ 在庫あり
$23.1 / 個
データシートを見る →EPM7128AETC144-10N
✅ ドロップイン✓ 在庫あり
$22.56 / 個
データシートを見る →EPM7128ATC144-10 最大定格＆電気的特性
| Manufacturer | Altera (now Intel) |
| Series | MAX 7000A |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Programmable Type | EE PLD (EEPROM-based, in-system programmable) |
| Macrocells | 128 |
| Logic Array Blocks | 4 |
| User I/O Pins | 68 |
| Propagation Delay (tPD) | 10 ns |
| Maximum Counter Frequency | 98 MHz |
| Supply Voltage - Internal (VCCINT) | 3.0 V to 3.6 V |
| I/O Voltage Levels | 5.0 V / 3.3 V / 2.5 V compatible (MultiVolt I/O) |
| In-System Programmability | Yes (IEEE Std 1149.1 JTAG) |
| 動作温度 | 0C to +70C (commercial) |
| パッケージ / ケース | 144-TQFP (20 x 20 mm) |
| 実装タイプ | Surface Mount |
| Architecture | Multiple Array Matrix (MAX), 2nd generation |
| RoHS ステータス | unknown (legacy Altera device) |
EPM7128ATC144-10 ピン構成
| ピン 1 | I/O — User I/O (Bank 1) |
| ピン 2 | I/O — User I/O (Bank 1) |
| ピン 3 | I/O — User I/O (Bank 1) |
| ピン 4 | I/O — User I/O (Bank 1) |
| ピン 5 | I/O — User I/O (Bank 1) |
| ピン 6 | I/O — User I/O (Bank 1) |
| ピン 7 | I/O — User I/O (Bank 1) |
| ピン 8 | I/O — User I/O (Bank 1) |
| ピン 9 | I/O — User I/O (Bank 1) |
| ピン 10 | GND — Ground |
| ピン 11 | I/O — User I/O (Bank 1) |
| ピン 12 | I/O — User I/O (Bank 1) |
| ピン 13 | I/O — User I/O (Bank 1) |
| ピン 14 | I/O — User I/O (Bank 1) |
| ピン 15 | I/O — User I/O (Bank 1) |
| ピン 16 | I/O — User I/O (Bank 1) |
| ピン 17 | I/O — User I/O (Bank 1) |
| ピン 18 | I/O — User I/O (Bank 1) |
| ピン 19 | GND — Ground |
| ピン 20 | I/O — User I/O (Bank 2) |
| ピン 21 | I/O — User I/O (Bank 2) |
| ピン 22 | I/O — User I/O (Bank 2) |
| ピン 23 | I/O — User I/O (Bank 2) |
| ピン 24 | I/O — User I/O (Bank 2) |
| ピン 25 | I/O — User I/O (Bank 2) |
| ピン 26 | I/O — User I/O (Bank 2) |
| ピン 27 | I/O — User I/O (Bank 2) |
| ピン 28 | I/O — User I/O (Bank 2) |
| ピン 29 | GND — Ground |
| ピン 30 | I/O — User I/O (Bank 2) |
| ピン 31 | I/O — User I/O (Bank 2) |
| ピン 32 | I/O — User I/O (Bank 2) |
| ピン 33 | I/O — User I/O (Bank 2) |
| ピン 34 | I/O — User I/O (Bank 2) |
| ピン 35 | I/O — User I/O (Bank 2) |
| ピン 36 | GND — Ground |
| ピン 37 | I/O — User I/O (Bank 3) |
| ピン 38 | I/O — User I/O (Bank 3) |
| ピン 39 | I/O — User I/O (Bank 3) |
| ピン 40 | I/O — User I/O (Bank 3) |
| ピン 41 | I/O — User I/O (Bank 3) |
| ピン 42 | I/O — User I/O (Bank 3) |
| ピン 43 | I/O — User I/O (Bank 3) |
| ピン 44 | I/O — User I/O (Bank 3) |
| ピン 45 | I/O — User I/O (Bank 3) |
| ピン 46 | GND — Ground |
| ピン 47 | I/O — User I/O (Bank 3) |
| ピン 48 | I/O — User I/O (Bank 3) |
| ピン 49 | I/O — User I/O (Bank 3) |
| ピン 50 | I/O — User I/O (Bank 3) |
| ピン 51 | I/O — User I/O (Bank 3) |
| ピン 52 | I/O — User I/O (Bank 3) |
| ピン 53 | I/O — User I/O (Bank 3) |
| ピン 54 | I/O — User I/O (Bank 3) |
| ピン 55 | GND — Ground |
| ピン 56 | I/O — User I/O (Bank 4) |
| ピン 57 | I/O — User I/O (Bank 4) |
| ピン 58 | I/O — User I/O (Bank 4) |
| ピン 59 | I/O — User I/O (Bank 4) |
| ピン 60 | I/O — User I/O (Bank 4) |
| ピン 61 | I/O — User I/O (Bank 4) |
| ピン 62 | I/O — User I/O (Bank 4) |
| ピン 63 | I/O — User I/O (Bank 4) |
| ピン 64 | I/O — User I/O (Bank 4) |
| ピン 65 | I/O — User I/O (Bank 4) |
| ピン 66 | GND — Ground |
| ピン 67 | I/O — User I/O (Bank 4) |
| ピン 68 | I/O — User I/O (Bank 4) |
| ピン 69 | I/O — User I/O (Bank 4) |
| ピン 70 | I/O — User I/O (Bank 4) |
| ピン 71 | I/O — User I/O (Bank 4) |
| ピン 72 | I/O — User I/O (Bank 4) |
| ピン 73 | TDI — JTAG Test Data In |
| ピン 74 | TMS — JTAG Test Mode Select |
| ピン 75 | TCK — JTAG Test Clock |
| ピン 76 | VCC — VCCINT (3.3 V core supply) |
| ピン 77 | VCC — VCCINT (3.3 V core supply) |
| ピン 78 | VCCIO — I/O supply Bank 1 |
| ピン 79 | VCCIO — I/O supply Bank 2 |
| ピン 80 | GND — Ground |
| ピン 81 | TDO — JTAG Test Data Out |
| ピン 82 | GCLK1 — Global Clock 1 |
| ピン 83 | GCLRn — Global Clear |
| ピン 84 | OE1 — Output Enable 1 |
| ピン 85 | OE2 — Output Enable 2 |
| ピン 86 | GND — Ground |
| ピン 87 | I/O — User I/O (Bank 1) |
| ピン 88 | I/O — User I/O (Bank 1) |
| ピン 89 | I/O — User I/O (Bank 1) |
| ピン 90 | I/O — User I/O (Bank 1) |
| ピン 91 | I/O — User I/O (Bank 1) |
| ピン 92 | I/O — User I/O (Bank 1) |
| ピン 93 | I/O — User I/O (Bank 1) |
| ピン 94 | I/O — User I/O (Bank 1) |
| ピン 95 | I/O — User I/O (Bank 1) |
| ピン 96 | I/O — User I/O (Bank 1) |
| ピン 97 | GND — Ground |
| ピン 98 | I/O — User I/O (Bank 1) |
| ピン 99 | I/O — User I/O (Bank 1) |
| ピン 100 | I/O — User I/O (Bank 1) |
| ピン 101 | I/O — User I/O (Bank 1) |
| ピン 102 | I/O — User I/O (Bank 1) |
| ピン 103 | I/O — User I/O (Bank 1) |
| ピン 104 | I/O — User I/O (Bank 1) |
| ピン 105 | I/O — User I/O (Bank 1) |
| ピン 106 | I/O — User I/O (Bank 1) |
| ピン 107 | GND — Ground |
| ピン 108 | I/O — User I/O (Bank 1) |
| ピン 109 | I/O — User I/O (Bank 1) |
| ピン 110 | I/O — User I/O (Bank 1) |
| ピン 111 | I/O — User I/O (Bank 1) |
| ピン 112 | I/O — User I/O (Bank 1) |
| ピン 113 | I/O — User I/O (Bank 1) |
| ピン 114 | I/O — User I/O (Bank 1) |
| ピン 115 | OE3 — Output Enable 3 |
| ピン 116 | OE4 — Output Enable 4 |
| ピン 117 | VCC — VCCINT (3.3 V core supply) |
| ピン 118 | VCC — VCCINT (3.3 V core supply) |
| ピン 119 | VCCIO — I/O supply Bank 3 |
| ピン 120 | VCCIO — I/O supply Bank 4 |
| ピン 121 | GND — Ground |
| ピン 122 | NC — Not connected |
| ピン 123 | NC — Not connected |
| ピン 124 | NC — Not connected |
| ピン 125 | NC — Not connected |
| ピン 126 | NC — Not connected |
| ピン 127 | NC — Not connected |
| ピン 128 | I/O — User I/O (Bank 2) |
| ピン 129 | I/O — User I/O (Bank 2) |
| ピン 130 | I/O — User I/O (Bank 2) |
| ピン 131 | I/O — User I/O (Bank 2) |
| ピン 132 | I/O — User I/O (Bank 2) |
| ピン 133 | I/O — User I/O (Bank 2) |
| ピン 134 | I/O — User I/O (Bank 2) |
| ピン 135 | I/O — User I/O (Bank 2) |
| ピン 136 | I/O — User I/O (Bank 2) |
| ピン 137 | GND — Ground |
| ピン 138 | I/O — User I/O (Bank 2) |
| ピン 139 | I/O — User I/O (Bank 2) |
| ピン 140 | I/O — User I/O (Bank 2) |
| ピン 141 | I/O — User I/O (Bank 2) |
| ピン 142 | I/O — User I/O (Bank 2) |
| ピン 143 | I/O — User I/O (Bank 2) |
| ピン 144 | GND — Ground |
主な用途
EPM7128ATC144-10 の用途: 6 件s: PCI-to-ISA Bus Bridge Glue Logic, Address Decoding & Chip-Select Generation, Peripheral I/O Expansion & Wake-Up Logic, LED Display & Multiplexed Scanner, Legacy TTL/CMOS Glue Logic Replacement, State Machine & Sequencer Implementation.
PCI-to-ISA Bus Bridge Glue Logic
The EPM7128ATC144-10 is widely deployed as 5V/3.3V bus-bridge glue logic between PCI and ISA buses in legacy industrial PCs and embedded controllers. Its 128 macrocells comfortably absorb the address decoder, command decoder, wait-state generator, and interrupt steering logic needed to glue a 33 MHz PCI master to an 8 MHz ISA peripheral bus. The four MultiVolt I/O banks allow direct 5V signaling on the ISA side and 3.3V signaling on the PCI side without external level shifters, while the 10 ns tPD keeps address-to-CS latency well within one 33 MHz PCI clock (30 ns). Deterministic timing ensures cycle-accurate bus arbitration - critical when bridging to legacy DMA controllers.
おすすめ
Address Decoding & Chip-Select Generation
The EPM7128ATC144-10 excels at generating chip-select (CS) and address-decoder outputs for microprocessors that lack enough native decoded outputs. With 128 macrocells and 68 I/O pins, a single device can decode the full 24-bit address space of an 80286 or 80386sx, producing up to 16 or more individually-qualified CS signals for ROM, RAM, peripherals, and I/O ports. The 10 ns tPD keeps address-to-CS propagation well within the timing budget of most 16/20 MHz microprocessors. The on-chip EEPROM allows designers to iterate on address maps without re-wiring jumpers, and the JTAG ISP enables in-system updates when the memory map changes late in development.
おすすめ
Peripheral I/O Expansion & Wake-Up Logic
In battery-powered industrial controllers, the EPM7128ATC144-10 serves as an ultra-low-power I/O expander and wake-up logic block. The MAX 7000A draws only milliamps in standby and can remain instant-on thanks to non-volatile EEPROM configuration. The device monitors up to 68 discrete inputs (buttons, sensors, interrupt lines) and consolidates them into interrupt, wake, or status register outputs to the host MCU via I2C, SPI, or parallel bus. The MultiVolt I/O lets a 3.3V MCU talk to 5V sensors directly, eliminating level-translator ICs.
おすすめ
LED Display & Multiplexed Scanner
The EPM7128ATC144-10 is a strong fit for LED display drivers, seven-segment multiplexers, and dot-matrix scanners used in industrial HMIs and digital signage. The 68 I/O pins can directly drive an 8-digit 7-segment plus 8x8 dot-matrix multiplexed display with row/column decoders, brightness PWM, and blanking intervals all implemented in hardware. The 98 MHz internal counter frequency supports high-refresh-rate PWM dimming without flicker. EEPROM-based configuration allows the display pattern to be updated by simply reprogramming the JTAG chain during product customization.
おすすめ
Legacy TTL/CMOS Glue Logic Replacement
A common modernization use case for the EPM7128ATC144-10 is replacing dozens of discrete 74LS/74HC/74F series TTL gates, latches, and decoders with a single CPLD. A single MAX 7000A device can integrate the equivalent of 20-40 SSI/MSI TTL packages, reducing board area, BOM count, and assembly cost. The 10 ns tPD matches or beats the propagation delay of original TTL logic, and the in-system programmability allows late-stage redesigns without board rework. Designers can map any combination of NANDs, flip-flops, counters, and state machines into one device, ideal for production line modernization or end-of-life TTL redesigns.
おすすめ
State Machine & Sequencer Implementation
The EPM7128ATC144-10 is well suited to implementing complex state machines, sequencers, and protocol controllers in industrial automation equipment. Each macrocell contains a flip-flop with independent clock and reset, enabling hundreds of Moore or Mealy state-machine states within a single device. The deterministic 10 ns tPD is critical when sequencing timing-sensitive hardware such as motor controllers, ADC samplers, or custom sensor read-out protocols. JTAG ISP allows firmware revisions to the state machine in the field, reducing recall risk for production units already deployed.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EPM7128ATC144-10 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EPM7128AETC144-10 | EPM7128AETC144-7N | EPM7128AETC144-7 | EPM7128AETI144-10N | EPM7128AETC144-10N |
|---|---|---|---|---|---|---|
| Package | 144-TQFP (20x20 mm) | 144-TQFP (20x20 mm) - same | 144-TQFP (20x20 mm) - same | 144-TQFP (20x20 mm) - same | 144-TQFP (20x20 mm) - same | 144-TQFP (20x20 mm) - same |
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Macrocells | 128 | 128 | 128 | 128 | 128 | 128 |
| User I/O Pins | 68 | 68 | 68 | 68 | 68 | 68 |
| Propagation Delay (tPD) | 10 ns | 10 ns | 7.5 ns | 7.5 ns | 10 ns | 10 ns |
| Max Counter Frequency | 98 MHz | 98 MHz | 125.5 MHz | 125.5 MHz | 98 MHz | 98 MHz |
| Operating Temperature | 0C to +70C (commercial) | -40C to +85C (industrial) | -40C to +85C (industrial) | -40C to +85C (industrial) | -40C to +85C (industrial) | -40C to +85C (industrial) |
| Core Voltage | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| Lead-Free (Pb-Free) | unknown | unknown | Yes (N suffix) | No | Yes (N suffix) | Yes (N suffix) |
| Series | MAX 7000A | MAX 7000A | MAX 7000A | MAX 7000A | MAX 7000A | MAX 7000A |
主な差別化要因
- Commercial-grade 0C to +70C operating temperature （vs EPM7128AETC144-10)
- 10 ns pin-to-pin propagation delay （vs EPM7128AETC144-7N)
- 68 user I/O pins - higher density than 100-pin MAX 7000A siblings （vs EPM7128ATC100-10)
設計ノート
Estimated: at typical 3.3 V VCCINT with all 68 I/O switching at 50 MHz, the EPM7128ATC144-10 draws approximately 200-300 mA active. Provide a minimum of one 0.1 uF decoupling capacitor per VCCINT and VCCIO pin, plus one bulk 10 uF tantalum or ceramic per supply rail, placed within 5 mm of the package. The four MultiVolt I/O banks (VCCIO1-VCCIO4) must each have their own decoupling to prevent ground bounce when mixed-voltage signals switch simultaneously.
Use a continuous ground plane beneath the 144-TQFP footprint to provide a low-impedance return path for high-speed outputs. Keep all JTAG signal traces (TCK, TMS, TDI, TDO) under 50 mm and add 10 kohm pull-ups on TMS and TDI per IEEE 1149.1 recommendations. The four output-enable pins (OE1-OE4) should be tied to logic-high via 4.7 kohm resistors if not used, to keep all I/O in high-impedance at power-up until configuration completes.
Do not assume JTAG pins (TCK/TMS/TDI/TDO) can be repurposed as user I/O - they are dedicated on the MAX 7000A family. Ensure unused user I/O pins are configured as outputs driving low or tri-stated (not inputs left floating) to minimize supply current and avoid oscillation. The GCLRn pin is a global clear and should be tied to VCCIO through a 4.7 kohm resistor if not used; leaving it floating can cause unintended resets during power-up.
コンプライアンス情報
Legacy Altera device with obsolete lifecycle status. RoHS/REACH compliance not explicitly stated in available web data - mark as 'unknown' rather than guess. The 'N' suffix on later variants (e.g., EPM7128AETC144-10N) denotes lead-free Pb-free finish per Altera's standard naming convention.
