EPM7128SLI84-10 - MAX 7000 CPLD 128MC 10ns 84-PLCC | Intel
部品番号: EPM7128SLI84-10 ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $12.45 | $12.45 |
| 10 | $11.2 | $112.00 |
| 100 | $9.85 | $985.00 |
| 500 | $8.5 | $4,250.00 |
| 1,000 | $7.25 | $7,250.00 |
EPM7128SLI84-10 概要
What is a CPLD? A Complex Programmable Logic Device is a non-volatile programmable logic IC that combines the architectural simplicity of a PAL/GAL with the density and flexibility of an FPGA for glue-logic, bus-interface, state-machine, and control-plane tasks. In the digital-system hierarchy, CPLDs sit between discrete 74-series glue logic and full FPGAs: they offer deterministic timing, instant-on from non-volatile memory, and pin-to-pin delays of a few nanoseconds - making them ideal for deterministic control logic rather than parallel data-path processing. The MAX 7000S family specifically targets 5 V system designs and remains a long-lived platform for industrial and legacy upgrades.
Key features include 128 macro cells, 68 available user I/Os, JTAG boundary-scan support compliant with IEEE Std 1149.1, multi-voltage I/O (5.0 V core with 3.3 V or 5.0 V interface), open-drain or totem-pole output options per pin, and programmable power-saving mode per macro cell. The 84-pin PLCC package provides through-hole or socket compatibility for legacy boards, while the in-system programmability via the ByteBlaster or ByteBlasterMV cable eliminates the need for a separate programmer.
Typical applications include 5 V industrial control boards, ISA/PCI bus-interface glue logic, address decoding, state-machine controllers, and legacy microprocessor peripheral interfaces where deterministic 10 ns timing and instant-on from EEPROM configuration are required.
When designing with this part, plan for the 5 V VCCINT requirement and consider the EPM7128SLI84-10N lead-free variant if RoHS compliance is mandatory for new designs.
This page synthesizes distributor pricing, drop-in 84-PLCC alternatives, and practical design notes not found in the original Altera datasheet.
ドロップイン代替品: EPM7128SLI84-10 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EPM7128SLI84-10 （同一形状・フットプリント） — 相違点: Mounting Type, Supply Voltage (VCCINT), Operating Temperature, Family, Package.
クイック比較ツール — 並列比較する代替部品を選択:
EPM7128SLI84-10N
✅ ドロップイン✓ 在庫あり
$8.45 / 個
データシートを見る →EPM7128SLC84-10
✅ ドロップイン✓ 在庫あり
$9.75 / 個
データシートを見る →EPM7128ELI84-20
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$7.95 / 個
データシートを見る →EPM7128ELC84-20
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$24.2 / 個
データシートを見る →EPM7128ELC84-10
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$7.2 / 個
データシートを見る →EPM7128AELC84-10N
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$10.45 / 個
データシートを見る →EPM7128SLI84-10 最大定格＆電気的特性
| Family | MAX 7000S |
| Usable Gates | 2.5K |
| Macro Cells | 128 |
| User I/Os | 68 |
| Logic Array Blocks (LABs) | 8 |
| Propagation Delay (tPD) | 10 ns |
| Internal Frequency | 100 MHz |
| Supply Voltage (VCCINT) | 5.0 V |
| Configuration Memory | EEPROM (in-system programmable) |
| 動作温度 | -40 °C to +85 °C (industrial) |
| パッケージ | 84-pin PLCC |
| 実装タイプ | Surface Mount / Socket |
| Process Technology | CMOS |
| JTAG Support | Yes (IEEE 1149.1) |
EPM7128SLI84-10 84-pin plcc ピン配置ガイド
EPM7128SLI84-10 (84-pin plcc パッケージ) のピン配置。 このデジタルICには、GPIO、通信インターフェース (UART、SPI、I2C)、および電源ピンが含まれています。代替ピン機能と設定オプションについては、メーカーのデータシートを参照してください。組み込みシステム設計とPCBレイアウトに不可欠です。
詳細なピン配置データはありません: EPM7128SLI84-10.
詳細は データシート をご参照ください。
主な用途
EPM7128SLI84-10 の用途: 6 件s: ISA/PCI Bus Address Decoding, 5 V Industrial Control Logic, Legacy Microprocessor Peripheral Interface, State Machine Controllers, Glue Logic Consolidation, Test & Measurement Equipment Front-End.
ISA/PCI Bus Address Decoding
The EPM7128SLI84-10 is well-suited for ISA/PCI bus address decoding on legacy 5 V industrial motherboards. Its 10 ns tPD supports the 8 MHz ISA bus cycle time with ample margin, while the 68 user I/Os accommodate full 24-bit address plus 16-bit data control. The 128 macro cells implement 8-16 independent chip-select decoders, each with registered outputs and bus-request acknowledge logic, replacing dozens of 74-series GAL/PAL devices with a single non-volatile part. The EEPROM configuration preserves decode maps across power cycles - critical for industrial PCs that must boot deterministic I/O maps.
おすすめ
5 V Industrial Control Logic
Industrial PLCs and motor-control boards benefit from the EPM7128SLI84-10's 5 V core and industrial -40 °C to +85 °C operating range. The 84-pin PLCC package is socket-compatible, enabling field replacement on legacy lines. Engineers use the 128 macro cells to implement PID control state machines, encoder-interface glue logic, and emergency-stop interlocks with deterministic 10 ns timing. The on-chip EEPROM stores configuration without an external boot ROM, and the JTAG ISP port allows firmware updates via the ByteBlaster cable without removing the part from the board.
おすすめ
Legacy Microprocessor Peripheral Interface
The EPM7128SLI84-10 serves as a flexible peripheral interface for 8/16-bit microprocessors such as 8051, Z80, or 68k family, providing wait-state generation, bus multiplexing, memory-bank switching, and interrupt prioritization. Its 10 ns propagation delay accommodates 25 MHz 68k bus cycles without wait states, while the 68 I/Os handle full address/data/control plus chip-select generation for up to 8 peripherals. The non-volatile EEPROM configuration means the boot memory map is set without an external PROM, simplifying BOM and shortening time-to-market.
おすすめ
State Machine Controllers
Designers use the EPM7128SLI84-10 to implement Moore and Mealy state machines for sequencing, traffic control, and protocol converters. With 128 macro cells each containing a flip-flop, the part can host 60-100 states with combinational output logic. The 10 ns tPD ensures state transitions complete within one 100 MHz clock cycle, enabling high-speed UART, SPI, or I2C bit-banging interfaces. ISP via JTAG permits state-table updates in the field without board removal, accelerating development iteration.
おすすめ
Glue Logic Consolidation
The EPM7128SLI84-10 consolidates 10-20 discrete 74HC/74LS logic gates into a single 84-PLCC, reducing board area and improving reliability. A typical use case is replacing address latches, bus transceivers, parity generators, and interrupt controllers in a 5 V embedded system. The non-volatile EEPROM configuration eliminates the need for a boot PROM, and the 10 ns timing matches HC-logic performance while drawing lower quiescent current. Engineers gain design flexibility - logic changes require only a JTAG re-flash, not a board respin.
おすすめ
Test & Measurement Equipment Front-End
Bench instruments and ATE fixtures use the EPM7128SLI84-10 for trigger conditioning, channel multiplexing, and pattern generation. The 68 user I/Os handle 32-channel logic-analyzer probe buffers or 16-channel digital-I/O multiplexing. The 10 ns propagation delay supports 50 MHz pattern-generation clock rates, while the industrial -40 °C to +85 °C range ensures operation in laboratory and factory environments. The non-volatile EEPROM configuration retains test patterns across power cycles - critical for production ATE where boot-time calibration is impractical.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EPM7128SLI84-10 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EPM7128SLI84-10N | EPM7128SLC84-10 | EPM7128ELI84-20 | EPM7128ELC84-20 | EPM7128ELC84-10 | EPM7128AELC84-10N |
|---|---|---|---|---|---|---|---|
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Package | 84-pin PLCC | 84-pin PLCC - same | 84-pin PLCC - same | 84-pin PLCC - same | 84-pin PLCC - same | 84-pin PLCC - same | 84-pin PLCC - same |
| Family | MAX 7000S | MAX 7000S - same | MAX 7000S - same | MAX 7000AE - different | MAX 7000AE - different | MAX 7000AE - different | MAX 7000AE - different |
| Core Voltage | 5.0 V | 5.0 V - same | 5.0 V - same | 3.3 V - different | 3.3 V - different | 3.3 V - different | 3.3 V - different |
| Propagation Delay | 10 ns | 10 ns - same | 10 ns - same | 20 ns - slower | 20 ns - slower | 10 ns - same | 10 ns - same |
| Macro Cells | 128 | 128 - same | 128 - same | 128 - same | 128 - same | 128 - same | 128 - same |
| Operating Temperature | -40 °C to +85 °C (industrial) | -40 °C to +85 °C - same | 0 °C to +70 °C - commercial | -40 °C to +85 °C - same | 0 °C to +70 °C - commercial | 0 °C to +70 °C - commercial | 0 °C to +70 °C - commercial |
| RoHS / Lead-Free | SnPb (non-RoHS) | Lead-free RoHS - compliant | SnPb (non-RoHS) | SnPb (non-RoHS) | SnPb (non-RoHS) | SnPb (non-RoHS) | Lead-free RoHS - compliant |
主な差別化要因
- Industrial temperature grade with 10 ns tPD （vs EPM7128SLC84-10)
- Direct drop-in for legacy non-RoHS assemblies （vs EPM7128SLI84-10N)
- 5 V core for legacy 5 V-only designs （vs EPM7128ELC84-10)
設計ノート
The EPM7128SLI84-10 requires a stable 5.0 V ±5% supply on VCCINT pins (typically pins 3, 17, 41, 65 on the 84-PLCC). Place 0.1 µF decoupling capacitors within 5 mm of each VCC pin and a 10 µF bulk tantalum at the board supply entry. Estimated quiescent current at 100 MHz is approximately 200 mA; in power-save mode (unused LABs disabled), this drops to ~50 mA. Do not share the 5 V analog supply with switching regulators - use a ferrite bead or LC filter if the system has noisy DC-DC converters nearby.
Do not substitute the EPM7128SLI84-10 (MAX 7000S, 5 V core) with the EPM7128ELC84-10 (MAX 7000AE, 3.3 V core) without reworking the board power supply - applying 5 V to a 3.3 V core device will damage it. Similarly, the -10N suffix denotes lead-free RoHS plating; the original -10 has SnPb leads. Verify your assembly process (reflow profile for SnPb vs lead-free) before placing the order.
The 84-pin PLCC has 0.05 inch (1.27 mm) pitch J-lead perimeter pads and an exposed die pad for thermal dissipation. Use a PLCC socket (e.g., 3M Textool or Aries) for prototype boards to enable ISP re-programming without desoldering. For production, SMT soldering to PLCC land patterns requires careful paste-stencil aperture design - J-lead fillets should be inspected per IPC-A-610 Class 2. Maintain 8 mil trace/space rules on I/O banks to accommodate 68 signal pins exiting the perimeter.
Route JTAG signals (TCK, TMS, TDI, TDO) with 50 Ω controlled impedance and keep them short (<50 mm) to avoid signal-integrity issues at high programming-clock rates. Place the JTAG header at the board edge for convenient ByteBlaster cable access. The global clock (GCLK) and clear (GCLRn) pins should be routed with ground shielding to minimize crosstalk, and any high-speed output enables (OE1, OE2) should be terminated with 100 Ω series resistors if driving long traces (>50 mm).
コンプライアンス情報
EPM7128SLI84-10 is non-RoHS due to SnPb lead finish; the -10N suffix denotes RoHS-compliant lead-free plating. Compliance status for REACH and conflict minerals was not available in the verified web data.
