EPM7128SQC160-10 - MAX 7000 CPLD, 128 Cells, 100 I/O, 10ns | Altera
MPN: EPM7128SQC160-10 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $24.5 | $24.50 |
| 10 | $21.8 | $218.00 |
| 100 | $18.95 | $1,895.00 |
| 250 | $16.4 | $4,100.00 |
| 500 | $14.2 | $7,100.00 |
Drop-in alternatives for EPM7128SQC160-10 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM7128SQC160-7N
β Drop-Inπ Reference alternative (not in catalog)
EPM7128SQC160-15
β Drop-Inβ In Stock
$9.95 / Unit
View Datasheet βEPM7128SQC160-10N
β Drop-Inβ In Stock
$9.2 / Unit
View Datasheet βEPM7128SQC160-7
β Drop-Inπ Reference alternative (not in catalog)
EPM7192SQC160-10
β Drop-Inπ Reference alternative (not in catalog)
EPM7128SQI160-10N
β Drop-Inπ Reference alternative (not in catalog)
EPM7128SQC160-10 Maximum Ratings & Electrical Characteristics
| Family | MAX 7000 |
| Series | MAX 7000S |
| Macro Cells | 128 |
| Usable Gates | 2,500 |
| Logic Array Blocks (LABs) | 8 |
| User I/O Pins | 100 |
| Maximum Operating Frequency | 100 MHz |
| Pin-to-Pin Propagation Delay (tPD) | 10 ns |
| Supply Voltage (VCCINT) | 5 V |
| I/O Supply Voltage (VCCIO) | 3.3 V or 5 V |
| Configuration Memory | Non-volatile EEPROM |
| Programming Interface | JTAG (IEEE 1149.1) / ByteBlaster |
| Package | 160-pin PQFP |
| Lead Pitch | 0.65 mm |
| Operating Temperature | 0C to +70C (commercial) |
| Mounting Type | Surface Mount |
| Compliance | RoHS - see notes |
EPM7128SQC160-10 Pin Configuration
| Pin 1 | I/O β User I/O pin |
| Pin 12 | TCK β JTAG Test Clock (IEEE 1149.1) |
| Pin 13 | TMS β JTAG Test Mode Select |
| Pin 14 | TDI β JTAG Test Data In |
| Pin 15 | VCCINT β 5V core supply |
| Pin 16 | I/O β User I/O pin |
| Pin 32 | GND β Ground |
| Pin 33 | I/O β User I/O pin |
| Pin 64 | GCLK1 β Global Clock input 1 |
| Pin 65 | GCLK2 β Global Clock input 2 |
| Pin 96 | OE1 β Global Output Enable 1 |
| Pin 97 | OE2 β Global Output Enable 2 |
| Pin 128 | CLR β Global Clear |
| Pin 129 | I/O β User I/O pin |
| Pin 160 | I/O β User I/O pin |
| Pin 161 | VCCIO β I/O supply voltage (3.3V or 5V) |
| Pin 162 | TDO β JTAG Test Data Out |
| Pin 163 | GND β Ground |
| Pin 164 | VCCINT β 5V core supply |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM7128SQC160-10 is suitable for 6 applications: PCI Bus Interface Bridging, Microcontroller Peripheral Expansion, Memory Address Decoding and Chip-Select Generation, Legacy Logic Replacement (74LS/74F/74HC Consolidation), State-Machine Controllers and Bus Arbiters, Industrial Control and Test Equipment.
PCI Bus Interface Bridging
The EPM7128SQC160-10 is well suited for 5V PCI 33 MHz bus interface bridging because of its 128 macro cells (enough to implement address/data multiplexers and command decoders), 100 MHz maximum toggle frequency, and PCI-compliant 5V-tolerant I/O drivers. The 10 ns pin-to-pin delay fits comfortably within the 33 MHz PCI 30 ns setup/hold budget when placed between a CPU local bus and a peripheral device. Use it to generate chip-select and wait-state signals, decode configuration cycles, and arbitrate bus masters without timing uncertainty. Compared to discrete 74F/74LS glue logic, the part reduces board area by 60-80% and consolidates revision logic in software.
Recommended
Microcontroller Peripheral Expansion
Use the EPM7128SQC160-10 to expand the peripheral count of legacy 8/16-bit microcontrollers (8051, 68k, ColdFire, Z80) that lack sufficient address-decoded chip-select lines or have limited general-purpose I/O. The device's 100 user I/O pins handle address latch demultiplexing, chip-select generation for external SRAM/Flash/EEPROM, and peripheral handshaking, all in one non-volatile, instantly-on package. The 10 ns tPD matches 25-40 MHz microcontroller bus speeds without wait states. Industrial designers prefer this part because it replaces 8-15 discrete 74HC logic packages while remaining 5V-tolerant, simplifying PCB routing and assembly.
Recommended
Memory Address Decoding and Chip-Select Generation
The EPM7128SQC160-10 excels at memory address decoding because its 128 macro cells can implement large multi-level AND/OR decode trees with predictable 10 ns propagation delay - critical when decoding a 24- or 32-bit address bus into 8-16 chip-select signals without glitches. The non-volatile EEPROM configuration means the decode map is preserved across power cycles, and JTAG in-system programmability allows last-minute memory-map changes without board rework. Engineers typically use this part to generate chip-selects for SRAM banks, Flash arrays, dual-port RAM, and boot ROM, replacing legacy 74LS138/139 decoder trees with a single device that occupies 1/10th the board area.
Recommended
Legacy Logic Replacement (74LS/74F/74HC Consolidation)
Designers use the EPM7128SQC160-10 to consolidate 20-60 discrete 74LS/74F/74HC logic packages into a single 160-pin PQFP device, dramatically reducing PCB area, assembly cost, and inventory SKUs. The CPLD's 2,500 usable gates and 100 user I/O pins can absorb entire glue-logic sections including address latches, transceivers, parity generators, and state-machine controllers. Because the configuration is EEPROM, the design is fixed at production time and requires no boot sequence. This is particularly valuable in industrial control boards, telecom line cards, and military/aerospace legacy upgrades where form-fit-function drop-in consolidation is required.
Recommended
State-Machine Controllers and Bus Arbiters
The EPM7128SQC160-10's 128 macro cells each contain a flip-flop, making the device ideal for implementing complex FSM controllers with 30-60 states, including bus arbiters, hand-shake sequencers, and protocol converters. Each macro cell provides a programmable register with clear, preset, and clock-enable controls, plus a sum-of-products logic array - exactly the primitives needed for Moore/Mealy state machines. The 100 MHz toggle frequency allows state transitions at bus-clock rates without metastability issues. Designers also appreciate the deterministic 10 ns routing delay, which simplifies static timing analysis compared to FPGA timing closure.
Recommended
Industrial Control and Test Equipment
The EPM7128SQC160-10 is widely deployed in industrial control boards, programmable logic controllers (PLCs), and automated test equipment (ATE) because of its 5V tolerance, commercial temperature range, and 10 ns deterministic timing. Use it to generate timing-critical waveforms, decode GPIB/VXI/I2C/SPI protocol signals, and consolidate discrete logic on backplanes that must operate for decades. The non-volatile EEPROM configuration ensures instant-on behavior at power-up, which is critical for safety interlocks. Long-term users continue to specify this part because of its known behavior and extensive library of reference designs in the MAX+PLUS II / Quartus II legacy ecosystem.
Recommended
Recommended Products Summary
Engineering reference data for EPM7128SQC160-10 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM7128SQC160-7N | EPM7128SQC160-15 | EPM7128SQC160-7 | EPM7128SQC160-10N | EPM7192SQC160-10 | EPM7128SQI160-10N |
|---|---|---|---|---|---|---|---|
| Package | PQFP-160 | PQFP-160 (same) | PQFP-160 (same) | PQFP-160 (same) | PQFP-160 (same) | PQFP-160 (same) | PQFP-160 (same) |
| Brand | Altera / Intel PSG | Altera / Intel PSG | Altera / Intel PSG | Altera / Intel PSG | Altera / Intel PSG | Altera / Intel PSG | Altera / Intel PSG |
| Macro Cells | 128 | 128 | 128 | 128 | 128 | 192 (+50%) | 128 |
| Pin-to-Pin Delay (tPD) | 10 ns | 7.5 ns (faster) | 15 ns (slower) | 7.5 ns (faster) | 10 ns (identical) | 10 ns (identical) | 10 ns (identical) |
| Max Toggle Frequency | 100 MHz | 125 MHz | 76.9 MHz | 125 MHz | 100 MHz | 100 MHz | 100 MHz |
| User I/O Pins | 100 | 100 | 100 | 100 | 100 | 124 | 100 |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C (commercial) | 0C to +70C (commercial) | 0C to +70C (commercial) | 0C to +70C (commercial) | 0C to +70C (commercial) | -40C to +85C (industrial) |
| Lead-Free / RoHS | See compliance notes | Lead-free N suffix | Standard (non-N) | Standard (non-N) | Lead-free N suffix | Standard (non-N) | Lead-free N suffix |
Key Differentiators
- Drop-in faster speed grade available in same package (vs EPM7128SQC160-7N)
- Higher logic density option in same package (vs EPM7192SQC160-10)
- Industrial temperature variant available (vs EPM7128SQI160-10N)
Design Notes
The 160-pin PQFP package has a 0.65 mm lead pitch - small enough that solder bridging is a real risk during reflow. Use a reflow profile with a 60-90 second soak between 150C and 200C to equalize pad temperatures, and verify pad geometry per IPC-7351 PQFP-160 guidelines. Stencil aperture reduction (4-mil reduction on each side) on fine-pitch pads reduces solder paste volume and bridging risk. Add thermal relief on the exposed pad if the part dissipates more than 1W continuous. Hand-soldering is not recommended for prototype work; use a hot-air rework station with PQFP-specific nozzles.
Quartus II support for legacy MAX 7000 devices requires the legacy device-support installer add-on - newer Quartus II releases dropped native MAX 7000 support. Download the add-on from Intel's archived downloads page and install it before opening any existing MAX+PLUS II designs. Also note that the EPM7128SQC160-10 is non-volatile (EEPROM) but the programming algorithm requires a specific JTAG IR instruction sequence; do not skip the ERASE-PROGRAM-VERIFY cycle or the configuration may be corrupted. For new designs, evaluate MAX II (EPM240) or MAX V (5M40ZE64) for active long-term supply.
The MAX 7000 I/O pins support user-programmable slew-rate control - enable slow slew rate on signals longer than 50 mm or that drive > 4 loads to reduce ground-bounce and EMI by 6-10 dB. Use fast slew rate only on clock and high-speed control signals. For multi-board designs where outputs drive backplane connectors, add 22-33 ohm series-termination resistors within 25 mm of the CPLD pin to dampen transmission-line reflections. Keep JTAG signals (TCK, TMS, TDI, TDO) away from clock and high-speed data traces to avoid programming failures during in-system programming.
Estimate: at 100 MHz toggle, all 100 I/O active, 5V VCCINT, the EPM7128SQC160-10 consumes approximately 250-400 mW steady-state. Decouple VCCINT with one 100 uF bulk capacitor plus four 0.1 uF ceramic capacitors placed within 5 mm of each VCCINT/GND pin pair (the PQFP-160 has multiple VCCINT and GND pins distributed around the package). Place a 10 uF tantalum plus a 0.1 uF ceramic on each VCCIO bank. Do not exceed the VCCINT absolute maximum of 7V or the part will suffer permanent damage.
Compliance Information
Standard EPM7128SQC160-10 (non-N suffix) contains lead and is not RoHS-compliant; the EPM7128SQC160-10N variant is the lead-free, RoHS-compliant alternative with identical electrical performance. AEC-Q100 qualification has not been pursued for the MAX 7000 family. REACH, halogen-free, and conflict-minerals status not verified in provided data - set to 'unknown'.
