EPM7128SQC160-15 - MAX 7000 CPLD, 128 Macrocells, 100 I/O | Intel
MPN: EPM7128SQC160-15 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.85 | $1,385.00 |
| 500 | $11.4 | $5,700.00 |
| 1,000 | $9.95 | $9,950.00 |
Drop-in alternatives for EPM7128SQC160-15 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM7128SQC160-10N
β Drop-Inβ In Stock
$9.2 / Unit
View Datasheet βEPM7128SQC160-10
β Drop-Inβ In Stock
$14.2 / Unit
View Datasheet βEPM7128SQC160-15 Maximum Ratings & Electrical Characteristics
| Series | MAX 7000 |
| Programmable Type | In-System Programmable (EEPROM) |
| Number of Macrocells | 128 |
| Number of Logic Elements/Blocks | 8 (LABs of 16 macrocells each) |
| Number of Usable Gates | 2,500 |
| Number of I/O | 100 |
| Propagation Delay (tpd) | 15 ns max |
| Logic Element Propagation Delay | 4.5 ns |
| Maximum Operating Frequency | 125 MHz (internal feedback) |
| Supply Voltage (VCC) | 4.75 V to 5.25 V |
| Logic Family | CMOS |
| Operating Temperature | 0C to +70C (commercial grade) |
| Package / Case | 160-BQFP (160-PQFP, 28x28 mm) |
| Mounting Type | Surface Mount |
| Programming Interface | IEEE 1149.1 JTAG |
| Configuration Memory | EEPROM (non-volatile, ~100 erase/program cycles) |
| Product Status | Obsolete (per distributor listings) |
EPM7128SQC160-15 Pin Configuration
| Pin 1 | I/O β User I/O pin (macrocell-controlled bidirectional) |
| Pin 2 | I/O β User I/O pin |
| Pin 3 | I/O β User I/O pin |
| Pin 4 | I/O β User I/O pin |
| Pin 5 | I/O β User I/O pin |
| Pin 6 | GND β Ground |
| Pin 7 | I/O β User I/O pin |
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| Pin 15 | I/O β User I/O pin |
| Pin 16 | GND β Ground |
| Pin 17 | I/O β User I/O pin |
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| Pin 25 | I/O β User I/O pin |
| Pin 26 | GND β Ground |
| Pin 27 | I/O β User I/O pin |
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| Pin 35 | I/O β User I/O pin |
| Pin 36 | GND β Ground |
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| Pin 46 | GND β Ground |
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| Pin 56 | GND β Ground |
| Pin 57 | I/O β User I/O pin |
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| Pin 66 | GND β Ground |
| Pin 67 | I/O β User I/O pin |
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| Pin 76 | GND β Ground |
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| Pin 86 | GND β Ground |
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| Pin 96 | GND β Ground |
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| Pin 106 | GND β Ground |
| Pin 107 | I/O β User I/O pin |
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| Pin 114 | I/O β User I/O pin |
| Pin 115 | I/O β User I/O pin |
| Pin 116 | GND β Ground |
| Pin 117 | TDI β JTAG Test Data In (IEEE 1149.1) |
| Pin 118 | TMS β JTAG Test Mode Select |
| Pin 119 | TCK β JTAG Test Clock |
| Pin 120 | VCC β 5V supply voltage |
| Pin 121 | I/O β User I/O pin |
| Pin 122 | I/O β User I/O pin |
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| Pin 128 | GND β Ground |
| Pin 129 | I/O β User I/O pin |
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| Pin 138 | GND β Ground |
| Pin 139 | I/O β User I/O pin |
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| Pin 148 | GND β Ground |
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| Pin 156 | I/O β User I/O pin |
| Pin 157 | I/O β User I/O pin |
| Pin 158 | GND β Ground |
| Pin 159 | TDO β JTAG Test Data Out (IEEE 1149.1) |
| Pin 160 | VCC β 5V supply voltage |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM7128SQC160-15 is suitable for 6 applications: Bus Interface Glue Logic, Address Decoding and Chip-Select Generation, Industrial Control State Machines, Legacy 74-Series Logic Replacement, Peripheral Control and Protocol Bridging, Test and Measurement Equipment Control.
Bus Interface Glue Logic
The EPM7128SQC160-15's deterministic 15 ns pin-to-pin delay and 100 I/Os make it ideal for bus-interface glue logic between microcontrollers, memories, and peripherals. Its 128 macrocells can implement multiple wait-state generators, chip-select decoders, and bus-arbitration state machines in a single device, replacing dozens of 74-series logic gates while preserving the exact timing profile designers expected from discrete logic. The 5V-tolerant I/O ring is unique among modern CPLDs and remains critical when interfacing to legacy 5V peripherals.
Recommended
Address Decoding and Chip-Select Generation
The EPM7128SQC160-15's 128 macrocells can decode a 32-bit address bus and generate up to 100 chip-select outputs with single-pass logic, ideal for memory maps in embedded systems and legacy PC/104 designs. Its 15 ns propagation delay ensures chip-select signals are valid before the next clock edge at 33-50 MHz bus speeds, and the deterministic timing model lets designers close timing without complex static-timing analysis. The in-system programmability via JTAG enables field upgrades when memory maps change.
Recommended
Industrial Control State Machines
The EPM7128SQC160-15's EEPROM-based non-volatile configuration and deterministic timing make it well-suited for industrial control state machines that must boot predictably at power-up with no external configuration memory. Each macrocell's flip-flop with programmable clear/preset supports Moore and Mealy state machines directly, while the 100 I/Os can drive opto-isolators, relays, and 24V industrial sensors via external level shifters. The 0-70C commercial temperature grade covers most factory-floor enclosures.
Recommended
Legacy 74-Series Logic Replacement
The EPM7128SQC160-15 consolidates 30-50 discrete 74LS/74HC logic gates into a single device, simplifying PCB layout, reducing BOM cost, and improving testability via JTAG boundary scan. Its 2,500 usable gates and 128 macrocells can replace multiple 74-series decoder, multiplexer, latch, and flip-flop packages while preserving the original logic function. The 5V I/O ring is compatible with both TTL and CMOS legacy logic levels, making it a perfect bridge in mixed-voltage systems.
Recommended
Peripheral Control and Protocol Bridging
The EPM7128SQC160-15 implements peripheral-control logic and protocol bridges (parallel-to-serial, I2C-to-SPI, UART-to-parallel) using its flexible macrocell flip-flops and AND-OR array. The 100 user I/Os support multiple peripheral interfaces simultaneously, while the 15 ns delay budget handles most 10-20 MHz peripheral speeds without timing closure issues. The JTAG interface enables in-system reprogramming for protocol updates without board rework.
Recommended
Test and Measurement Equipment Control
The EPM7128SQC160-15's deterministic timing model and JTAG boundary-scan support make it valuable in test-and-measurement equipment where repeatable timing and board-level test access are essential. Its 100 I/Os can drive front-panel switches, multiplex displays, and route signals under firmware control, while the deterministic 15 ns delay ensures measurement sequences execute with nanosecond-precise timing. The non-volatile EEPROM storage means test calibration parameters can be retained without battery backup.
Recommended
Recommended Products Summary
Engineering reference data for EPM7128SQC160-15 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM7128SQC160-10N | EPM7128SQC160-10 | EPM7128AETC100-10 | EPM7128BTC100-10 | EPM7128ATC100-10 | EPM7128SQC100-15 |
|---|---|---|---|---|---|---|---|
| Package | 160-BQFP (PQFP-160, 28x28 mm) | 160-BQFP (PQFP-160, 28x28 mm) - same | 160-BQFP (PQFP-160, 28x28 mm) - same | 100-TQFP - different package | 100-TQFP - different package | 100-TQFP - different package | 100-PQFP - different package |
| Brand | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) |
| Family | MAX 7000 | MAX 7000 | MAX 7000 | MAX 7000A | MAX 7000B | MAX 7000A | MAX 7000 |
| Macrocells | 128 | 128 (same) | 128 (same) | 128 (same) | 128 (same) | 128 (same) | 128 (same) |
| Usable Gates | 2,500 | 2,500 (same) | 2,500 (same) | 2,500 (same) | 2,500 (same) | 2,500 (same) | 2,500 (same) |
| User I/O | 100 | 100 (same) | 100 (same) | 84 (-16%) | 84 (-16%) | 84 (-16%) | 84 (-16%) |
| Propagation Delay (tpd) | 15 ns | 10 ns (-33%, faster) | 10 ns (-33%, faster) | 10 ns (-33%, faster) | 10 ns (-33%, faster) | 10 ns (-33%, faster) | 15 ns (same) |
| Supply Voltage | 5V (4.75-5.25V) | 5V (same) | 5V (same) | 3.3V (different) | 2.5V (different) | 3.3V (different) | 5V (same) |
| Configuration Memory | EEPROM | EEPROM (same) | EEPROM (same) | EEPROM (same) | EEPROM (same) | EEPROM (same) | EEPROM (same) |
Key Differentiators
- 5V-tolerant I/O ring across 100 user I/Os (vs MAX 7000A variants (EPM7128AETC100-10))
- Deterministic 15 ns pin-to-pin timing (vs EPM7128SQC160-10N (10 ns version))
- Largest 160-pin PQFP package with 100 I/Os (vs EPM7128SQC100-15 (100-pin PQFP))
Design Notes
The EPM7128SQC160-15 requires a stable 5V supply (4.75V to 5.25V) with decoupling capacitors placed close to every VCC pin. According to the Altera datasheet, each VCC pin should have a 0.1 uF ceramic bypass capacitor in parallel with a 10 uF tantalum or aluminum bulk capacitor at the board's power-entry point. Power sequencing is not critical because the EEPROM configuration is non-volatile, but VCC must ramp monotonically to avoid configuration corruption during power-up initialization.
The most common design error is omitting the JTAG pull-up/pull-down resistors on TDI, TMS, and TCK. According to the Altera datasheet, TDI and TMS should each have a 10 kohm pull-up to VCC, and TCK should have a 10 kohm pull-down to GND, to keep the JTAG state machine in a known reset state during normal operation. Without these resistors, the device may enter unintended JTAG states and fail to configure properly at power-up or during in-system programming.
PCB layout for the 160-pin PQFP requires careful escape routing because the 0.65 mm pin pitch leaves only 0.25 mm clearance between traces. According to the Altera datasheet, use 0.15 mm trace width with 0.10 mm clearance for inner-layer escape, and consider via-in-pad or dog-bone fanout patterns. Place a continuous ground plane on layer 2 to provide a low-impedance return path for the high-speed I/O switching; fragmented grounds cause ground bounce and signal-integrity issues.
Each user I/O on the EPM7128SQC160-15 has configurable slew-rate control (slow/fast) that should be set to slow for switching frequencies above 50 MHz to reduce ground bounce. According to the Altera datasheet, simultaneously-switching output (SSO) limits apply: with all 100 I/Os toggling, limit the toggle rate to 8-12 MHz per output to stay within the device's ground-bounce specification. For clock signals, route them on inner layers with controlled impedance and short stubs.
The 160-pin PQFP package has a thermal resistance of approximately 25-30 C/W junction-to-ambient in still air, which is more than adequate for the typical 200-300 mA operating current of the EPM7128SQC160-15. Estimated: power dissipation at 5V x 200 mA = 1.0 W gives a 25-30 C junction temperature rise above ambient. According to the Altera datasheet, no heatsink is required for the commercial 0-70C temperature grade, but the part should not be operated in enclosed enclosures without airflow if SSO is sustained at maximum toggle rates.
Compliance Information
RoHS compliance status not confirmed in verified web data; the original 160-pin PQFP package is a through-hole-era footprint that may be non-RoHS. AEC-Q100 not applicable for commercial-grade CPLD. Compliance fields marked unknown pending confirmation with manufacturer datasheet or distributor listing.
