H58G66CK8BX147N - 8GB LPDDR5X-8533 DRAM FBGA-315 | SK hynix
部品番号: H58G66CK8BX147N ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $42.5 | $42.50 |
| 10 | $40.8 | $408.00 |
| 100 | $38.9 | $3,890.00 |
| 500 | $36.75 | $18,375.00 |
| 1,000 | $34.6 | $34,600.00 |
H58G66CK8BX147N 概要
LPDDR5X (Low Power Double Data Rate 5X) is the extended-speed evolution of the LPDDR5 standard defined by JEDEC. As a class of synchronous dynamic random-access memory, LPDDR devices prioritize power efficiency and bandwidth-per-watt over the absolute latency of desktop DDR, placing them in the memory IC hierarchy: SDRAM -> DDR SDRAM -> LPDDR family -> LPDDR5/LPDDR5X. LPDDR5X raises signaling rates beyond the 6400 Mbps of LPDDR5 while retaining the low-voltage 1.05 V-class core supply, making it the dominant memory type for flagship smartphones, AI edge accelerators, and automotive infotainment.
Key features of the H58G66CK8BX147N include its 64Gb density in a single monolithic die-class package, an x8 I/O organization suited to 64-bit bus designs using eight devices, LPDDR5X-8533 operation for maximum bandwidth, and dynamic voltage/frequency scaling inherited from the LPDDR5 architecture. Deep power-down and per-bank refresh modes minimize standby current in battery-operated systems.
Technically, the device is specified in SK hynix 315-ball FBGA documentation, which defines requirements for JEDEC-compliant x16 and x8 single-channel SDRAM devices. Bank groups, burst lengths, and DVFSC/DVFSQ operation follow the LPDDR5 JEDEC protocol, with the X-speed bin extending CAS latency tables for 8533 Mbps operation.
Typical applications include flagship smartphone SoC memory, AI edge computing modules, tablet and notebook DRAM-down designs, and automotive ADAS compute platforms where memory bandwidth per watt is the limiting factor.
Designers should pay close attention to fly-by command/address routing, on-die termination settings, and controller training algorithms, since LPDDR5X at 8533 Mbps leaves minimal timing margin; silicon-proven controller support and re-training routines are essential.
This page synthesizes distributor availability data, the SK hynix FBGA specification PDF, drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
ドロップイン代替品: H58G66CK8BX147N — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: H58G66CK8BX147N （同一形状・フットプリント） — 相違点: Memory Type, Organization, Density, Package, Application Domain.
クイック比較ツール — 並列比較する代替部品を選択:
H58G66CK8BX147
✅ ドロップイン✓ 在庫あり
価格はお問い合わせください
データシートを見る →H58G56AK6QX032N
✅ ドロップイン✓ 在庫あり
$13.4 / 個
データシートを見る →H58G56AK6QX032
✅ ドロップイン✓ 在庫あり
$20.6 / 個
データシートを見る →H58G46AK6QX033
✅ ドロップイン✓ 在庫あり
$9.75 / 個
データシートを見る →H58G46AK6PX033N
✅ ドロップイン✓ 在庫あり
価格はお問い合わせください
データシートを見る →MT62F3G32D8DV-023
✅ ドロップイン✓ 在庫あり
$55.7 / 個
データシートを見る →MT53E2G64D8TN-046
✅ ドロップイン✓ 在庫あり
価格はお問い合わせください
データシートを見る →H58G66CK8BX147N 最大定格＆電気的特性
| メモリタイプ | LPDDR5X SDRAM |
| Density | 64 Gbit (8 GB) |
| メモリ構成 | x8 (single channel) |
| Maximum Data Rate | 8533 Mbps |
| Supply Voltage Domain | 0.5 V to 1.8 V |
| Core Voltage Class | 1.05 V (LPDDR5/LPDDR5X class) |
| パッケージ | 315-ball FBGA |
| 実装タイプ | Surface Mount |
| Standard Compliance | JEDEC-compliant single-channel SDRAM (per SK hynix 315-ball FBGA specification) |
| インターフェース | LPDDR5/LPDDR5X protocol |
| Channel Configuration | Single channel (x8 or x16 capable family) |
| Power Management | Dynamic voltage and frequency scaling (DVFSC/DVFSQ) |
| Application Domain | Smartphone, AI edge, server-class mobile computing |
| Refresh Scheme | LPDDR5 per-bank / all-bank refresh |
H58G66CK8BX147N 315-ball fbga ピン配置ガイド
H58G66CK8BX147N (315-ball fbga パッケージ) のピン配置。 このデジタルICには、GPIO、通信インターフェース (UART、SPI、I2C)、および電源ピンが含まれています。代替ピン機能と設定オプションについては、メーカーのデータシートを参照してください。組み込みシステム設計とPCBレイアウトに不可欠です。
詳細なピン配置データはありません: H58G66CK8BX147N.
詳細は データシート をご参照ください。
主な用途
H58G66CK8BX147N の用途: 6 件s: Flagship Smartphone DRAM, AI Edge Computing Modules, Tablet and Notebook DRAM-Down Memory, Automotive ADAS and Cockpit Compute, 5G Networking and Edge Servers, AR/VR and Wearable Headsets.
Flagship Smartphone DRAM
Flagship smartphones pair high-core-count SoCs with 8GB to 18GB of LPDDR5/5X memory, and the H58G66CK8BX147N directly serves this market with 8GB per package at up to 8533 Mbps. Its x8 organization allows an eight-device, 64-bit bus that delivers peak bandwidth above 68 GB/s, enough to feed 4K camera pipelines, on-device large-language-model inference, and high-refresh displays simultaneously. The 0.5 V I/O domain and DVFSC/DVFSQ dynamic voltage-frequency scaling cut idle and active power, extending battery life where DRAM is a top-three power consumer. Place devices on a fly-by CA bus with on-die termination enabled and follow controller training routines for X speed bins.
おすすめ
AI Edge Computing Modules
Edge AI accelerators for vision, robotics, and on-device generative models are bandwidth-starved, and the H58G66CK8BX147N addresses this with LPDDR5X-8533 signaling. At 8533 Mbps on a x8 device, an eight-chip bank provides the tens of GB/s that transformer and CNN workloads demand, while the 1.05 V-class core keeps energy per bit low for fanless enclosures. Typical deployments place four to eight packages around an NPU SoC on tightly length-matched fly-by routing. Because 8533 Mbps operation leaves little timing margin, designers should budget controller re-training across temperature and validate signal integrity on 8-layer or better stackups with solid VDDQ planes.
おすすめ
Tablet and Notebook DRAM-Down Memory
Thin tablets and fanless notebooks use DRAM-down LPDDR5X soldered on the main board instead of SO-DIMM modules to save z-height and power. The 8GB H58G66CK8BX147N lets a two-package configuration reach 16GB with a 128-bit or split bus, achieving desktop-class memory bandwidth for productivity and content-creation workloads at LPDDR5X power levels. DVFSC/DVFSQ lets the platform drop to low-voltage states during light use, important for always-on PCs. Layout practice: use per-byte differential DQS pairs, keep CA stubs short with fly-by topology, and follow the SK hynix 315-ball FBGA specification for ball assignment and decoupling recommendations.
おすすめ
Automotive ADAS and Cockpit Compute
ADAS domain controllers and digital cockpits fuse multi-camera sensor input with AI perception, requiring memory bandwidth that only LPDDR5X-class DRAM provides in the power envelope of a vehicle. The H58G66CK8BX147N supplies 8GB per package at up to 8533 Mbps, allowing sensor-frame buffers and neural-network weight storage without switching to power-hungry GDDR. Thermal design is decisive: cabin electronics see -40C to +105C ambient extremes, so derate speed bins at temperature and confirm the appropriate qualification level with SK hynix. XAIPART recommends verifying the automotive qualification suffix or applying system-level functional-safety measures before deployment in safety-critical paths.
おすすめ
5G Networking and Edge Servers
5G small-cell basebands, RAN accelerators, and edge servers increasingly adopt LPDDR5X as main memory where DIMM slots are absent. The H58G66CK8BX147N offers a JEDEC-compliant, single-channel x8 device that scales to multi-package banks, delivering the random-access bandwidth for packet processing, MACsec, and lightweight AI inference at the network edge. Its LPDDR5X-8533 rate sustains line-rate forwarding with headroom for telemetry. Designers should implement per-bank refresh scheduling to bound worst-case latency for deterministic networking and use the deep power-down modes in standby paths. Verify memory-controller support for X speed bins and ECC-over-run schemes in the target SoC before layout freeze.
おすすめ
AR/VR and Wearable Headsets
Standalone AR and VR headsets render dual high-resolution displays at 90-120 Hz while running inside-out tracking, making memory bandwidth the primary bottleneck. The H58G66CK8BX147N provides 8GB of LPDDR5X at up to 8533 Mbps, enough to sustain simultaneous display composition and pose-estimation pipelines within the strict thermal budget of a head-worn device. The 0.5 V I/O domain minimizes trace switching power, and DVFSC allows graceful bandwidth-power trade-offs during less demanding scenes. Use short, tightly matched fly-by routing on flex-rigid boards and enable controller refresh-aware scheduling to prevent frame drops during refresh bursts at high operating temperatures.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: H58G66CK8BX147N — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | H58G66CK8BX147 | H58G56AK6QX032N | MT62F3G32D8DV-023 |
|---|---|---|---|---|
| Package | 315-ball FBGA | 315-ball FBGA - same | 315-ball FBGA - same family | FBGA LPDDR5X ball map - verify variant |
| Brand | SK hynix | SK hynix | SK hynix | Micron Technology |
| Density | 64 Gbit (8 GB) | 64 Gbit (8 GB) | Lower LPDDR5-class density | Multi-die aggregate (24 Gbit-class x32 package) |
| Memory Standard | LPDDR5X | LPDDR5X | LPDDR5 | LPDDR5X |
| Maximum Data Rate | 8533 Mbps | 8533 Mbps | LPDDR5-class (up to 6400 Mbps) | 8533 Mbps-class (-023 speed bin) |
| JEDEC Compliance | Yes (single-channel x8/x16 per FBGA spec) | Yes | Yes (LPDDR5) | Yes (LPDDR5X) |
主な差別化要因
- LPDDR5X-8533 speed grade （vs H58G56AK6QX032N)
- Full 8GB density per package （vs H58G46AK6QX033)
- Single-channel JEDEC x8 simplicity （vs MT62F3G32D8DV-023)
設計ノート
At 8533 Mbps, LPDDR5X trace budgets are extremely tight. Route CA and DQ on fly-by/point-to-point topologies with length matching within a few mils per byte lane, reference DQ routing to a continuous VDDQ plane, and use on-die termination (ODT) settings from the SK hynix 315-ball FBGA specification. Simulate eye diagrams at the X speed bin across corner temperature, and plan for controller re-training routines because 8533 Mbps operation typically requires periodic training updates in the field.
The device spans 0.5 V to 1.8 V supply domains: a 1.05 V-class core (VDD2/VDD1) and a ~0.5 V VDDQ. Provide independent, low-noise DC-DC rails with fast transient response, since LPDDR5X load current can step between deep power-down and full-bandwidth bursts in microseconds. Use DVFSC/DVFSQ to trade bandwidth for power dynamically, but sequence voltage changes per the JEDEC LPDDR5 protocol - never scale rails independently of controller commands.
Decouple each FBGA-315 package with multiple 100 nF ceramic capacitors on VDDQ plus bulk capacitance near the PMIC, placed within 2 mm of the ball field. Keep the DRAM within approximately 50 mm of the SoC at 8533 Mbps; longer routes force lower speed bins. Follow the ball assignment in the H58G66CK8BX147 specification exactly - LPDDR5 ball maps are not interchangeable with LPDDR4 footprints, and a mis-mapped CA/DQ net will fail training irrecoverably.
コンプライアンス情報
Compliance data not stated in provided sources; JEDEC-compliant protocol per SK hynix 315-ball FBGA specification. Automotive AEC-Q100 qualification not indicated in available data.