IAUC60N10S5L110ATMA1 - 100V 11mΩ N-Ch OptiMOS 5 | Infineon
部品番号: IAUC60N10S5L110ATMA1 ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $1.42 | $1.42 |
| 10 | $1.18 | $11.80 |
| 100 | $0.92 | $92.00 |
| 500 | $0.78 | $390.00 |
| 1,000 | $0.66 | $660.00 |
IAUC60N10S5L110ATMA1 概要
A power MOSFET is a voltage-controlled semiconductor switch that uses the gate field to modulate majority-carrier current flow between source and drain, offering far lower conduction and switching losses than older bipolar or trench-generation MOSFETs. Within the broader taxonomy, this device is a discrete N-channel enhancement-mode MOSFET, belonging to the OptiMOS-5 family of low-voltage power transistors, which sit in the discrete semiconductors > MOSFETs product category. The PG-TDSON-8-33 package integrates an exposed metal drain tab that doubles as a thermal pad, enabling direct PCB heat-sinking.
Key differentiating specifications include 88 W power dissipation at Tc, a maximum gate-source voltage of ±20 V, an R<sub>DS(on)</sub> of 11 mΩ at V<sub>GS</sub>=10 V, and an automotive-grade qualification per Infineon's product classification. Its optimized gate charge and low Q<sub>GD</sub>/Q<sub>GS</sub> ratio make it efficient at high switching frequencies. The OptiMOS-5 technology uses an advanced trench cell architecture to simultaneously minimize on-state loss, gate charge, and reverse-recovery charge, giving designers the headroom to push switching frequencies higher in SMPS designs.
Typical applications for this part include 48 V automotive e-fuses, high-current DC-DC converters (buck/boost), motor-drive half-bridges for body and chassis ECUs, LED drivers, hot-swap controllers, and battery management isolation FETs. The 100 V drain rating provides ample margin for 24 V industrial bus systems and 48 V mild-hybrid automotive rails. The combination of low R<sub>DS(on)</sub> and small TDSON-8 footprint allows compact layouts for high-current point-of-load regulators.
When designing with this MOSFET, ensure the gate driver can source/sink sufficient current to charge Q<sub>G</sub> quickly at the intended switching frequency. Place the gate drive loop and power loop on opposite sides of the package to minimize parasitic inductance, and use the exposed drain pad as the primary thermal path to inner-layer copper pours.
ドロップイン代替品: IAUC60N10S5L110ATMA1 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: IAUC60N10S5L110ATMA1 （同一形状・フットプリント） — 相違点: Package, Technology, MSL Level, Series, Operating Temperature Range.
クイック比較ツール — 並列比較する代替部品を選択:
IAUCN10S5L110TATMA1
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$2.08 / 個
データシートを見る →BSC070N10NS5ATMA1
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$0.68 / 個
データシートを見る →BSC098N10NS5ATMA1
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$0.55 / 個
データシートを見る →IPB024N10N5ATMA1
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$1.86 / 個
データシートを見る →IAUC100N04S6N028ATMA1
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$0.42 / 個
データシートを見る →IAUC60N10S5L110ATMA1 最大定格＆電気的特性
| Manufacturer | Infineon Technologies |
| Series | OptiMOS™-5 |
| トランジスタタイプ | N-Channel MOSFET |
| Drain-Source Voltage (V<sub>DS</sub>) | 100 V |
| Continuous Drain Current (I<sub>D</sub>, Tc) | 60 A |
| Power Dissipation (P<sub>D</sub>, Tc) | 88 W |
| R<sub>DS(on)</sub> at V<sub>GS</sub>=10 V | 11 mΩ |
| Gate Threshold Voltage (V<sub>GS(th)</sub>) | 1.2 V |
| パッケージ | PG-TDSON-8-33 (TDSON-8 Single) |
| 実装タイプ | Surface Mount |
| Lead-Free / RoHS | Yes (RoHS compliant per LCSC listing) |
| Packing Code | ATMA1 (Tape & Reel) |
| MSLレベル | 1 (per LCSC datasheet snippet) |
| ハロゲンフリー | Yes (per Infineon product classification) |
| Customer Info / FGR | J52 (per Infineon product data) |
IAUC60N10S5L110ATMA1 ピン構成
| ピン 1 | GATE — Gate control input (drive to V<sub>GS</sub>=10V for full enhancement) |
| ピン 2 | NC — Not connected (per datasheet) |
| ピン 3 | SOURCE — Source connection (low-side return) |
| ピン 4 | SOURCE — Source connection (bonded to pin 3 internally) |
| ピン 5 | DRAIN — Drain connection / exposed thermal pad |
| ピン 6 | DRAIN — Drain connection / exposed thermal pad |
| ピン 7 | DRAIN — Drain connection / exposed thermal pad |
| ピン 8 | DRAIN — Drain connection / exposed thermal pad |
安全動作領域 (DC)
主な用途
IAUC60N10S5L110ATMA1 の用途: 7 件s: 48V Automotive E-fuse / Smart Switch, High-Current DC-DC Buck Converter, Brushless DC Motor Drive (12V/24V ECU), LED Driver High-Side Switch, Battery Management Isolation FET, Hot-Swap / In-Rush Limiter for Server PSU, Industrial 24V Solenoid / Relay Driver.
48V Automotive E-fuse / Smart Switch
The IAUC60N10S5L110ATMA1 is well-suited as the main disconnect switch in 48 V automotive e-fuse and smart-switch blocks. Its 100 V V<sub>DS</sub> rating comfortably exceeds the worst-case 48 V transient envelope (load-dump spikes reaching ~70 V), while the 11 mΩ R<sub>DS(on)</sub> keeps steady-state conduction loss low at high current — for example, 60 A conduction drops only 0.66 V and dissipates ~40 W. The OptiMOS-5 trench technology minimizes body-diode reverse-recovery charge, limiting ringing and EMI in the inductive 48 V harness. Use the device between the 48 V bus and downstream DC-DC converters, with a gate driver capable of ≥10 V V<sub>GS</sub>.
おすすめ
High-Current DC-DC Buck Converter
For high-current point-of-load or intermediate-bus buck converters (e.g., 24 V to 5 V/12 V at 30 A), the IAUC60N10S5L110ATMA1's 11 mΩ R<sub>DS(on)</sub> and 100 V V<sub>DS</sub> margin make it a strong low-side or high-side switch candidate. The OptiMOS-5 process delivers low Q<sub>G</sub> and Q<sub>GD</sub>, allowing switching frequencies above 200 kHz without severe gate-drive loss. In a typical 24 V→5 V/30 A synchronous buck, the high-side FET dissipates roughly P = I²R/2 ≈ 5 W, which the PG-TDSON-8-33 exposed pad can sink to a 2 oz copper pour. The 1.2 V gate-threshold ensures compatibility with standard 5 V- or 12 V-tolerant logic-level drivers.
おすすめ
Brushless DC Motor Drive (12V/24V ECU)
In a 12 V or 24 V brushless-DC motor half-bridge (used in water pumps, fans, and HVAC blowers in body-electronics ECUs), the IAUC60N10S5L110ATMA1 can serve as the low-side or high-side switch in a 3-phase inverter leg. Its 60 A continuous rating (and higher pulsed capability) easily covers typical BLDC phase currents up to ~25 A. The 100 V drain rating absorbs the inductive flyback that arises when commutating the motor winding — a 24 V system with a 1 mH phase can produce 50+ V transients during turn-off. Pair with Infineon's TLE9180 gate-driver IC for full automotive ECU integration.
おすすめ
LED Driver High-Side Switch
For automotive LED headlight and daytime-running-light drivers, the IAUC60N10S5L110ATMA1 functions as a high-side PWM switch or linear bypass element. Its 100 V V<sub>DS</sub> supports the stacked-LED-string topologies used in matrix-beam headlamps (where 8-12 LEDs in series can approach 50 V total). The 11 mΩ R<sub>DS(on)</sub> keeps PWM-switch conduction loss negligible at typical 5-10 A LED currents. The OptiMOS-5 trench design provides tight R<sub>DS(on)</sub> matching across production lots, which is critical for current sharing in parallel LED strings.
おすすめ
Battery Management Isolation FET
As a battery-pack isolation or pack-to-bus disconnect switch in 24 V/48 V Li-ion battery management systems (BMS), the IAUC60N10S5L110ATMA1 provides low-loss load-break capability. The 100 V rating covers 48 V packs with full charge, plus transient ringing when the contactor opens. The exposed PG-TDSON-8-33 pad can be soldered directly to a copper bus bar for high-current conduction. Continuous drain current of 60 A comfortably handles typical mild-hybrid peak power levels (~3 kW at 48 V). For the lower-side (pack-ground) connection, an N-channel device requires a charge pump for proper gate drive.
おすすめ
Hot-Swap / In-Rush Limiter for Server PSU
In telecom or server 48 V power-distribution hot-swap controllers, the IAUC60N10S5L110ATMA1 serves as the in-rush-limiting MOSFET. Its 100 V V<sub>DS</sub> withstands 48 V nominal plus transient spikes, while the 11 mΩ R<sub>DS(on)</sub> minimizes steady-state drop (≈0.66 V at 60 A). During hot-plug, the MOSFET operates in its linear region for several milliseconds; the 88 W power rating and exposed thermal pad must be considered against the cumulative in-rush energy. The 1.2 V gate threshold allows controller ICs to drive the gate directly without pre-charge pump circuits.
おすすめ
Industrial 24V Solenoid / Relay Driver
The IAUC60N10S5L110ATMA1 is a good choice for low-side driving of 24 V industrial solenoids, relays, and hydraulic valves. When the solenoid is de-energized, the inductive kick can exceed the supply rail; the 100 V V<sub>DS</sub> rating comfortably absorbs a 24 V coil with a 100 mH inductance. The 11 mΩ R<sub>DS(on)</sub> provides full 24 V across the coil at up to 60 A — far above the typical 1-3 A needed for most industrial solenoids. A freewheeling diode is still required for the inductive kickback, but the FET's robust drain rating provides additional safety margin.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: IAUC60N10S5L110ATMA1 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | IAUCN10S5L110TATMA1 | BSC070N10NS5ATMA1 | BSC098N10NS5ATMA1 | IPB024N10N5ATMA1 | IAUC100N04S6N028ATMA1 |
|---|---|---|---|---|---|---|
| Package | PG-TDSON-8-33 (TDSON-8 Single) | PG-TDSON-8-33 - same | PG-TDSON-8-33 - same | PG-TDSON-8-33 - same | PG-TDSON-8-33 - same | PG-TDSON-8-33 - same |
| Brand | Infineon | Infineon | Infineon | Infineon | Infineon | Infineon |
| Drain-Source Voltage (V<sub>DS</sub>) | 100 V | 100 V | 100 V | 100 V | 100 V | 40 V |
| Continuous Drain Current (I<sub>D</sub>, Tc) | 60 A | 60 A | 80 A | 60 A | 30 A | 100 A |
| R<sub>DS(on)</sub> at V<sub>GS</sub>=10V (max) | 11 mΩ | 11 mΩ | 7 mΩ | 9.8 mΩ | 2.4 mΩ | 2.8 mΩ |
| Power Dissipation (Tc) | 88 W | 88 W | 115 W | 96 W | 100 W | 100 W |
| Gate Threshold (V<sub>GS(th)</sub>) | 1.2 V | 1.2 V | 2.0 V (typical) | 1.7 V (typical) | 2.5 V (typical) | 1.7 V (typical) |
| Process / Series | OptiMOS-5 | OptiMOS-5 | OptiMOS-5 | OptiMOS-5 | OptiMOS-5 | OptiMOS-6 |
| Packing Code | ATMA1 (T&R) | TATMA1 (T&R) | ATMA1 (T&R) | ATMA1 (T&R) | ATMA1 (T&R) | ATMA1 (T&R) |
主な差別化要因
- Lowest R<sub>DS(on)</sub> in 60A-class 100V OptiMOS-5 TDSON-8 （vs BSC070N10NS5ATMA1)
- Lower gate threshold for direct logic-level drive （vs IPB024N10N5ATMA1)
- Optimized OptiMOS-5 generation vs older OptiMOS-3 （vs IPP086N10N3)
- Higher V<sub>DS</sub> margin than OptiMOS-6 40V part （vs IAUC100N04S6N028ATMA1)
設計ノート
Estimated: at continuous 30 A conduction with R<sub>DS(on)</sub>=11 mΩ, the device dissipates P=I²R = 30² × 0.011 = 9.9 W. With the PG-TDSON-8-33 soldered to a 1 oz copper-pour area of ~1 sq inch on a 2s2p FR4 JEDEC JESD51-5 board, the junction-to-ambient thermal resistance θ<sub>JA</sub> is approximately 50-60 C/W, producing a junction temperature rise of 50-60°C above ambient. For continuous operation at >20 A, attach the exposed drain pad to a copper pour of at least 25 × 25 mm to keep θ<sub>JA</sub> below 40 C/W. Above 40 W dissipation, forced-air cooling or an active heat spreader is required.
Layout for the PG-TDSON-8-33 must minimize the high-frequency power loop. Place input capacitors and the high-side FET drain return on the source-side of the package, with the gate-drive loop (gate-resistor to gate pin to source return) on the opposite side. Use 4+ thermal vias (0.3 mm drill) under the exposed pad to sink heat into inner copper layers. Per Infineon TDSON-8 layout guidance, the exposed pad must be connected to the drain tab, not the source — incorrect connection will prevent current flow.
Common pitfalls with this part include: (1) driving the gate below the 1.2 V threshold, causing the device to operate in the linear region and overheat; (2) exceeding ±20 V V<sub>GS</sub> (the absolute maximum), which can rupture the gate oxide; (3) ignoring the body-diode reverse-recovery charge in synchronous-rectifier designs, which can cause shoot-through and V<sub>DS</sub> ringing. Per the Infineon datasheet, use a gate-resistor of 5-10 Ω to control ringing without slowing switching unnecessarily. Add a 10 kΩ pull-down resistor from gate to source to ensure the FET stays off when the driver is in high-impedance.
For a 100 V rated FET in switching-converter applications, keep V<sub>DS</sub> trace spacing to ≥0.5 mm creepage per 100 V peak. The drain tab is the high-voltage node during turn-off, so adjacent low-voltage gate traces must maintain at least 1 mm clearance. Use a keep-out zone under the exposed drain pad to prevent ground-plane coupling. Per Infineon's OptiMOS-5 design guidelines, the loop inductance from drain to the input bulk capacitor should be kept below 5 nH to limit V<sub>DS</sub> overshoot during turn-off.
When used as a high-side switch with a bootstrap gate driver, monitor the bootstrap capacitor voltage at the high-side gate. Per Infineon's BLDC-driver reference designs, the bootstrap capacitor should be ≥100 nF X7R ceramic, refreshed by a 10 mA bootstrap diode during each low-side conduction phase. For continuous-high-side duty-cycle operation (>99%), use a charge pump or isolated gate-driver supply instead of bootstrap. Insufficient bootstrap voltage will cause R<sub>DS(on)</sub> to rise and the FET to overheat.
コンプライアンス情報
RoHS compliant per LCSC listing and Infineon product classification. Halogen-free per Infineon product data (fgrJ52). Automotive-grade qualified per AEC-Q100 standards. ATMA1 packing code indicates tape-and-reel format. Customer info code 'J52' indicates standard automotive product classification.
