ADC1213D105HN-C1 - Dual 12-bit 105MSPS ADC | Renesas | JESD204A
부품 번호: ADC1213D105HN-C1 ✓ 활성| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $34.2 | $342.00 |
| 100 | $28.95 | $2,895.00 |
| 500 | $24.1 | $12,050.00 |
| 1,000 | $20.5 | $20,500.00 |
ADC1213D105HN-C1 개요
A pipelined ADC is a high-speed converter type using multiple cascaded low-resolution stages to achieve fast conversion with moderate die area and power. It sits within the data acquisition converter family alongside successive-approximation (SAR) and flash ADCs, and is the dominant architecture for communications infrastructure, medical imaging, and defense signal chains where sample rates from 10 MSPS to several hundred MSPS are required with 8-14 bit resolution.
Key specifications for the ADC1213D105HN-C1 include dual 12-bit resolution at 105 MSPS per channel, 56-VFQFPN exposed-pad package, JESD204A serial output interface, and a single 1.8 V analog/digital supply rail. The pipelined core supports simultaneous sampling on both channels with low latency, and the JESD204A interface provides deterministic multi-lane serial data transport to an FPGA or ASIC receiver.
Typical applications include multi-antenna wireless base stations, medical ultrasound beamformers, radar and electronic-warfare receivers, high-speed data acquisition cards, and broadband software-defined radio front ends. The serial JESD204A link pairs naturally with Xilinx Kintex/Virtex and Altera Stratix/Cyclone FPGAs that include hard JESD204 transceivers.
When designing with this part, pay attention to the JESD204A lane count and required reference clock for the link, and follow the reference decoupling scheme in the datasheet closely because the serializer is jitter-driven.
드롭인 대체품: ADC1213D105HN-C1 — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: ADC1213D105HN-C1 (동일 폼 팩터 및 풋프린트) — 차이점: Input Type, Package, Number of Channels, Data Interface, Resolution.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
ADC1213D065HN-C1
✅ 드롭인✓ 재고 있음
$21.5 / 개
데이터시트 보기 →ADC1213D080HN-C1
✅ 드롭인✓ 재고 있음
$23.1 / 개
데이터시트 보기 →ADC1213D125HN-C1
✅ 드롭인✓ 재고 있음
$31.2 / 개
데이터시트 보기 →ADC1112D125HN-C18
✅ 드롭인✓ 재고 있음
$9.48 / 개
데이터시트 보기 →ADC1012D1240527020HN/C1:5
✅ 드롭인 ⚠️ 사양 미검증📋 참조 대체품 (카탈로그에 없음)
ADC1213D105HN-C1 최대 정격 & 전기적 특성
| 분해능 | 12 bits per channel (dual channel) |
| Sample Rate (per channel) | 105 MSPS |
| Family Speed Grades | 65 / 80 / 105 / 125 MSPS |
| Number of Channels | 2 (simultaneous sampling) |
| Architecture | Pipelined |
| Data Interface | Serial JESD204A |
| 패키지 | 56-VFQFPN (8x8 mm) with EP |
| 핀 수 | 56 |
| Analog Supply Voltage | 1.8 V (typical) |
| Digital Supply Voltage | 1.8 V (typical) |
| Input Type | Differential analog inputs |
| 실장 유형 | Surface Mount |
| RoHS 상태 | Compliant |
ADC1213D105HN-C1 핀 구성
| 핀 1 | GND — Ground reference |
| 핀 2 | VA19 — Analog 1.8 V supply |
| 핀 3 | INA+ — Channel A positive analog input |
| 핀 4 | INA- — Channel A negative analog input |
| 핀 5 | VCM_A — Channel A common-mode voltage |
| 핀 6 | GND — Ground |
| 핀 7 | INB+ — Channel B positive analog input |
| 핀 8 | INB- — Channel B negative analog input |
| 핀 9 | VCM_B — Channel B common-mode voltage |
| 핀 10 | VA19 — Analog 1.8 V supply |
| 핀 11 | GND — Ground |
| 핀 12 | VD19 — Digital 1.8 V supply |
| 핀 13 | GND — Ground |
| 핀 14 | CLKP — Differential clock positive input |
| 핀 15 | CLKN — Differential clock negative input |
| 핀 16 | GND — Ground |
| 핀 17 | SYNCBP — JESD204A SYNCB positive (request for K28.3 characters) |
| 핀 18 | SYNCBN — JESD204A SYNCB negative |
| 핀 19 | RESETB — Active-low reset input |
| 핀 20 | PDWNB — Active-low power-down input |
| 핀 21 | CSB — SPI chip-select (active low) |
| 핀 22 | SCLK — SPI serial clock |
| 핀 23 | SDIO — SPI serial data I/O |
| 핀 24 | SDO — SPI serial data out |
| 핀 25 | GND — Ground |
| 핀 26 | VD19 — Digital 1.8 V supply |
| 핀 27 | DOUT0P — JESD204A lane 0 positive output |
| 핀 28 | DOUT0N — JESD204A lane 0 negative output |
| 핀 29 | DOUT1P — JESD204A lane 1 positive output |
| 핀 30 | DOUT1N — JESD204A lane 1 negative output |
| 핀 31 | DOUT2P — JESD204A lane 2 positive output |
| 핀 32 | DOUT2N — JESD204A lane 2 negative output |
| 핀 33 | DOUT3P — JESD204A lane 3 positive output |
| 핀 34 | DOUT3N — JESD204A lane 3 negative output |
| 핀 35 | VD19 — Digital 1.8 V supply |
| 핀 36 | GND — Ground |
| 핀 37 | NC — Not connected (per datasheet) |
| 핀 38 | NC — Not connected (per datasheet) |
| 핀 39 | NC — Not connected (per datasheet) |
| 핀 40 | NC — Not connected (per datasheet) |
| 핀 41 | NC — Not connected (per datasheet) |
| 핀 42 | NC — Not connected (per datasheet) |
| 핀 43 | NC — Not connected (per datasheet) |
| 핀 44 | NC — Not connected (per datasheet) |
| 핀 45 | NC — Not connected (per datasheet) |
| 핀 46 | NC — Not connected (per datasheet) |
| 핀 47 | GND — Ground |
| 핀 48 | VA19 — Analog 1.8 V supply |
| 핀 49 | GND — Ground |
| 핀 50 | VA19 — Analog 1.8 V supply |
| 핀 51 | VREF — Voltage reference bypass |
| 핀 52 | GND — Ground |
| 핀 53 | NC — Not connected (per datasheet) |
| 핀 54 | NC — Not connected (per datasheet) |
| 핀 55 | NC — Not connected (per datasheet) |
| 핀 56 | EPAD — Exposed thermal pad - solder to ground |
일반적인 애플리케이션
ADC1213D105HN-C1 적합 용도: 6 애플리케이션s: Wireless Base Station Receiver, Medical Ultrasound Beamformer, Radar and Electronic Warfare Receiver, High-Speed Data Acquisition Card, Broadband Software Defined Radio, Communications Test Equipment.
Wireless Base Station Receiver
The ADC1213D105HN-C1 is well-suited for multi-antenna wireless base station receivers where dual-channel 12-bit 105 MSPS sampling captures I/Q base-band signals from each antenna branch. The JESD204A serial output streams data into Xilinx Kintex or Altera Stratix FPGAs that include hard JESD204 transceivers, reducing FPGA pin count and PCB routing complexity. With 1.8 V single-supply operation the device integrates cleanly into the radio card's power tree alongside low-noise LDOs. Differential analog inputs accept direct connections from the preceding IQ demodulator with minimal interface circuitry. The pipelined core delivers the SFDR and SNR required for LTE and 5G NR receiver signal chains at 105 MSPS.
추천
Medical Ultrasound Beamformer
The ADC1213D105HN-C1's dual-channel simultaneous sampling and 12-bit resolution are ideal for medical ultrasound beamforming front ends where each channel digitizes the RF output of an ultrasonic transducer. 105 MSPS per channel provides sufficient bandwidth for high-frequency imaging probes while the JESD204A interface streams the digitized RF into an FPGA-based beamformer. Low power consumption at 1.8 V supply keeps per-channel thermal dissipation low, important for dense multi-element probe arrays. The exposed-pad 56-VFQFPN package allows tight PCB layout for probe-head integration. The pipelined core's low latency enables real-time image reconstruction in clinical ultrasound systems.
추천
Radar and Electronic Warfare Receiver
The ADC1213D105HN-C1 suits radar and electronic-warfare receivers where dual 12-bit channels at 105 MSPS capture base-band I/Q from each antenna element. The JESD204A interface simplifies routing across densely populated phased-array boards, while the pipelined core's low latency supports pulse-Doppler signal processing. Differential analog inputs accept direct connection to mixers in the receiver chain, preserving SNR through to the FPGA. The exposed-pad package provides thermal headroom for sustained operation in ruggedized defense electronics. Renesas' proven supply chain and long-term product support make it appropriate for defense programs with multi-year deployment horizons.
추천
High-Speed Data Acquisition Card
The ADC1213D105HN-C1 integrates two synchronized 12-bit ADC channels into a single package, simplifying high-speed data acquisition card design for test and measurement, instrumentation, and broadband recorders. At 105 MSPS per channel, the device captures signals with Nyquist bandwidth of 50 MHz per channel, while the JESD204A serial interface transports data into the host FPGA for buffering to DDR memory. Single 1.8 V supply operation reduces power tree complexity compared to multi-rail ADC solutions. The exposed-pad 56-VFQFPN package accommodates standard reflow assembly. Pin-compatibility with the ADC1213D family allows the same PCB to populate 65/80/105/125 MSPS speed grades.
추천
Broadband Software Defined Radio
The ADC1213D105HN-C1 enables software-defined radio (SDR) platforms where dual 12-bit 105 MSPS channels digitize I/Q base-band from a tunable RF front end. The JESD204A interface minimizes FPGA pin usage and PCB trace count, critical for portable battery-powered SDR designs. 1.8 V operation allows direct LDO regulation from a single lithium-ion cell or USB bus power. The pipelined core provides deterministic latency suitable for protocol-aware base-band processing. The exposed-pad package supports both commercial and ruggedized enclosures. With cross-brand second sources and Renesas-original long-term support, the part is attractive for both prototype and production SDR platforms.
추천
Communications Test Equipment
The ADC1213D105HN-C1 fits communications test equipment such as signal analyzers, base-station testers, and protocol conformance systems where dual channels of 12-bit 105 MSPS digitization are required. The JESD204A interface connects directly to test-instrument FPGAs that perform FFT, demodulation, and protocol decoding in real time. Differential analog inputs accept direct connection to the instrument's RF down-conversion stage with minimal signal conditioning. The exposed-pad 56-VFQFPN package supports dense multi-channel instrument front ends. Pin-compatibility across the ADC1213D family allows the same hardware platform to address different market segments with different sample-rate requirements.
추천
추천 제품 요약
엔지니어링 참조 데이터: ADC1213D105HN-C1 — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | ADC1213D065HN-C1 | ADC1213D080HN-C1 | ADC1213D125HN-C1 |
|---|---|---|---|---|
| Brand | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics |
| Package | 56-VFQFPN (8x8 mm) with EP | 56-VFQFPN (8x8) - same | 56-VFQFPN (8x8) - same | 56-VFQFPN (8x8) - same |
| Resolution | 12 bits per channel | 12 bits | 12 bits | 12 bits |
| Sample Rate (per channel) | 105 MSPS | 65 MSPS (-38%) | 80 MSPS (-24%) | 125 MSPS (+19%) |
| Number of Channels | 2 (simultaneous) | 2 | 2 | 2 |
| Architecture | Pipelined | Pipelined | Pipelined | Pipelined |
| Digital Interface | JESD204A serial | JESD204A | JESD204A | JESD204A |
| Supply Voltage | 1.8 V single rail | 1.8 V | 1.8 V | 1.8 V |
주요 차별점
- Pin-compatible speed-grade flexibility across the ADC1213D family (vs ADC1213D125HN-C1)
- Dual-channel simultaneous sampling in a single package (vs Two discrete single-channel ADCs)
- JESD204A serial interface eliminates wide parallel LVDS bus (vs Parallel LVDS output ADCs)
설계 노트
Decouple the 1.8 V analog and digital rails with a 10 uF bulk ceramic plus 0.1 uF and 1 nF high-frequency ceramics placed within 2 mm of each supply pin. Place a ferrite bead or pi-filter between the analog and digital 1.8 V rails to prevent digital switching noise from coupling into the analog front-end. Use a low-noise LDO such as LT3042 or ADP1763 upstream to preserve SNR and SFDR at 105 MSPS. Reference: Renesas ADC1213D datasheet recommended power tree.
Solder the exposed thermal pad (pin 56) to a continuous ground copper pour of at least 1 square inch to keep junction temperature within ratings. At full-speed 105 MSPS dual-channel operation the device dissipates sufficient power that without adequate thermal relief junction temperature may rise above 85C ambient capability. Estimated thermal resistance for the 56-VFQFPN is around 25 C/W with a properly soldered thermal pad.
Route the analog inputs (INA+/-, INB+/-) as a 100-ohm differential pair with matched length to within 0.5 mm, and keep them isolated from digital JESD204A output traces by at least 3x the dielectric thickness. Maintain 90-ohm differential impedance for JESD204A serial output lanes (DOUT0P/N..DOUT3P/N) and 100-ohm differential for the CLKP/N clock input. Place the clock generation circuitry (typically a low-jitter PLL or VCXO) close to the CLKP/N pins to minimize jitter contribution.
Always configure the JESD204A link parameters (L, M, F, K, N, N') to match the FPGA/ASIC receiver before issuing SYNCB. Mismatched link parameters are the most common first-power-on failure. Do not leave the SYNCBP/N pins floating - they require proper LVDS termination. The CSB pin must be driven high (de-asserted) after SPI configuration writes to prevent accidental re-configuration. Reference: Renesas ADC1213D datasheet JESD204A configuration section.
규정 준수 정보
RoHS and REACH compliant per Renesas product page. Industrial temperature grade (-40C to +85C); not AEC-Q100 qualified - not intended for automotive safety applications.
