BSZ100N03MSGATMA1 - 30V N-Ch OptiMOS 40A TSDSON-8 MOSFET | Infineon
부품 번호: BSZ100N03MSGATMA1 ✓ 활성| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $0.95 | $0.95 |
| 10 | $0.82 | $8.20 |
| 100 | $0.71 | $71.00 |
| 500 | $0.58 | $290.00 |
| 1,000 | $0.49 | $490.00 |
| 3,000 | $0.41 | $1,230.00 |
BSZ100N03MSGATMA1 개요
A power MOSFET is the fundamental switching element in modern switch-mode power supplies (SMPS); in SMPS taxonomy, it sits under synchronous rectifier -> power MOSFET -> discrete semiconductor -> power management IC. The OptiMOS family is specifically engineered for low-voltage, high-frequency step-down converters where conduction loss, switching loss and figure-of-merit (FOM = RDS(on) x Qg) dominate system efficiency. The BSZ100N03MS uses trench MOSFET technology, which reduces cell pitch and on-resistance per unit silicon area.
Key features include a typical RDS(on) in the single-digit milliohm range at VGS=10 V, low gate charge Qg for fast switching transitions, integrated body diode for synchronous-rectifier operation, and 100% avalanche-tested ruggedness per JEDEC target-application qualification. Pb-free plating, halogen-free molding compound per IEC 61249-2-21, and RoHS compliance make it suitable for environmentally restricted designs.
The device is qualified to JEDEC standards for target applications, supports superior thermal resistance through its exposed-die TSDSON pad, and is rated for 2.1 W power dissipation at TA and 30 W at TC, enabling compact high-density layouts. Compared to standard MOSFETs, the low FOM enables higher switching frequencies (multi-MHz operation), reducing the size of inductors and output capacitors in the surrounding converter.
Typical applications include high-efficiency synchronous buck converters in servers, datacom/telecom point-of-load (POL) regulators, notebook voltage rails, USB-PD and DC-DC modules, and motor-drive low-side switches. In SMPS designs, two BSZ100N03MS devices typically form a half-bridge: one as the high-side control FET and one as the low-side synchronous rectifier.
When designing with this part, place it on a substantial copper pour (typically >6 cm² drain area on FR4) to achieve the rated thermal performance, keep the gate-drive loop compact to minimize switching loss, and ensure VGS does not exceed the ±20 V absolute maximum. Avoid body-diode conduction under continuous high dV/dt, as this can trigger unwanted turn-on in the high-side FET.
This page synthesizes distributor pricing, parametric drop-in alternatives, and practical layout/thermal design notes that are not collated in the manufacturer datasheet alone, providing distinct value for engineers selecting a 30 V N-channel MOSFET in TSDSON-8.
드롭인 대체품: BSZ100N03MSGATMA1 — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: BSZ100N03MSGATMA1 (동일 폼 팩터 및 풋프린트) — 차이점: Configuration, MSL Level, Package, Technology, FET Type.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
BSZ100N03MS
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
BSC076N04NDATMA1
✅ 드롭인✓ 재고 있음
$0.82 / 개
데이터시트 보기 →BSC050N04LSGATMA1
✅ 드롭인✓ 재고 있음
$0.41 / 개
데이터시트 보기 →IAUC60N04S6L030HATMA1
✅ 드롭인 ⚠️ 사양 미검증✓ 재고 있음
$0.94 / 개
데이터시트 보기 →NTMFS4984N
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
FDMS3660S
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
BSZ100N03MSGATMA1 최대 정격 & 전기적 특성
| Manufacturer | Infineon Technologies |
| Part Family | OptiMOS 25V / 30V |
| 트랜지스터 유형 | N-Channel MOSFET |
| Configuration | Single with built-in body diode |
| Maximum Drain-Source Voltage (VDS) | 30 V |
| Continuous Drain Current (ID) at TA | 10 A |
| Continuous Drain Current (ID) at TC | 40 A |
| Power Dissipation (PD) at TA | 2.1 W |
| Power Dissipation (PD) at TC | 30 W |
| Technology | Trench MOSFET (OptiMOS) |
| 실장 유형 | Surface Mount |
| 패키지 | PG-TSDSON-8 (5x6 mm) |
| Terminal Finish | Tin (Pb-free) |
| 동작 온도 범위 | -55C to +150C (junction) |
| Qualification | JEDEC - target application qualified |
| Avalanche Tested | 100% (per JEDEC) |
| RoHS Compliance | Compliant (Pb-free plating) |
| 할로겐 프리 | Yes (per IEC 61249-2-21) |
| MSL 레벨 | MSL1 (per JEDEC J-STD-020) |
BSZ100N03MSGATMA1 핀 구성
| 핀 1 | G — Gate - gate drive input |
| 핀 2 | S — Source - low-side return path |
| 핀 3 | S — Source - low-side return path |
| 핀 4 | S — Source - low-side return path |
| 핀 5 | S — Source - low-side return path |
| 핀 6 | S — Source - low-side return path |
| 핀 7 | D — Drain - high-voltage switching node |
| 핀 8 | D — Drain - high-voltage switching node |
일반적인 애플리케이션
BSZ100N03MSGATMA1 적합 용도: 6 애플리케이션s: Synchronous Buck Converter (Server POL), Notebook Voltage Regulator (5V Gate Drive), USB-PD and DC-DC Module, Motor Drive Low-Side Switch, Hot-Swap / eFuse Switch (Low-Side), Battery Management System (1S-3S Li-ion Protection).
Synchronous Buck Converter (Server POL)
The BSZ100N03MSGATMA1 is purpose-built for synchronous buck converters in 12 V input server and datacom point-of-load (POL) regulators. Its 30 V VDS provides ample headroom for 12 V bus transients, while the OptiMOS low FOM (Qg x RDS(on)) enables switching frequencies above 500 kHz, shrinking output inductors and capacitors. Two BSZ100N03MSGATMA1 devices form the half-bridge - one high-side control FET and one low-side synchronous rectifier - delivering 95%+ efficiency at 20-40 A loads typical of CPU/GPU core rails.
추천
Notebook Voltage Regulator (5V Gate Drive)
Optimized for 5 V gate-drive notebook and ultrabook voltage rails, the BSZ100N03MSGATMA1 delivers the low on-state resistance and minimal gate charge required by 1S-3 MHz buck regulators on the main system bus. In a typical 19 V to 5 V/3.3 V notebook POL, it operates as the low-side synchronous rectifier, reducing conduction loss and improving light-load efficiency when paired with Infineon's OptiMOS high-side FET. The PG-TSDSON-8 footprint enables compact layouts beneath BGA CPU packages.
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USB-PD and DC-DC Module
The BSZ100N03MSGATMA1 is well-suited for USB-Power-Delivery (USB-PD 3.1) and standalone DC-DC modules operating from 5 V, 9 V, 12 V, or 20 V input buses. Its 30 V VDS tolerates USB-PD 28 V extended-power transients with adequate margin, while the 40 A TC current rating supports 100 W class output power levels (20 V/5 A). The TSDSON-8 (5x6 mm) footprint allows integration into small-form-factor GaN-replacement modules and compact adapter designs.
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Motor Drive Low-Side Switch
For low-side switching in brushed DC and stepper motor driver stages up to 24 V, the BSZ100N03MSGATMA1 provides 40 A peak handling and avalanche-rated robustness for the inductive kick during PWM chopping. The integrated body diode supports slow-decay current recirculation in H-bridge configurations. For 3-phase BLDC drives, two or three BSZ100N03MSGATMA1 form the lower half of the inverter bridge, with matched upper-half FETs from the same OptiMOS family.
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Hot-Swap / eFuse Switch (Low-Side)
In low-side hot-swap and electronic-fuse (eFuse) circuits for 12 V server backplanes and battery-protected loads, the BSZ100N03MSGATMA1 acts as the disconnect switch, with its avalanche-tested 30 V VDS handling inrush transients during card insertion. The exposed-drain TSDSON-8 pad enables high-current-density thermal management on FR4 with appropriate copper. Pair with a hot-swap controller such as the BTS51202EKAXUMA1 or TPS259x for SOA protection and current-limit foldback.
추천
Battery Management System (1S-3S Li-ion Protection)
The BSZ100N03MSGATMA1 functions as a low-side protection FET in 1S-3S Li-ion battery management systems, where the 30 V VDS tolerates the 12.6 V maximum charge voltage of a 3S pack plus transient spikes. Its low RDS(on) minimizes voltage drop during high-current discharge (notebook, power-tool, e-bike applications), improving runtime and reducing thermal dissipation. The halogen-free, RoHS-compliant packaging aligns with IEC 62133 and UN 38.3 transportation requirements.
추천
추천 제품 요약
엔지니어링 참조 데이터: BSZ100N03MSGATMA1 — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | BSZ100N03MS | BSC076N04NDATMA1 | BSC050N04LSGATMA1 | NTMFS4984N | FDMS3660S |
|---|---|---|---|---|---|---|
| Brand | Infineon Technologies | Infineon Technologies | Infineon Technologies | Infineon Technologies | onsemi | onsemi |
| Package | PG-TSDSON-8 (5x6 mm) | PG-TSDSON-8 (5x6 mm) - same | PG-TSDSON-8 (5x6 mm) - same | PG-TSDSON-8 (5x6 mm) - same | SO-8FL / TSDSON-equivalent (5x6 mm) - same | Power 56 (5x6 mm) - same |
| VDS (max) | 30 V | 30 V | 40 V | 40 V | 30 V | 30 V |
| Technology | OptiMOS 25V/30V (Trench) | OptiMOS 25V/30V (Trench) | OptiMOS (Trench) | OptiMOS (Trench) | onsemi N-ch trench | onsemi PowerTrench |
| Optimized Gate Drive | 5 V | 5 V | 10 V (full enhancement at 10V) | 10 V | 10 V | 10 V |
| Target Application | Server POL, Notebook, VGA | Server POL, Notebook, VGA | Server POL, 24V bus | Server POL, higher current | Synchronous rectification | Synchronous rectification, OR-ing |
주요 차별점
- Optimized for 5V gate drive with industry-leading FOM (vs BSC076N04NDATMA1 (40V Infineon OptiMOS))
- 30V VDS optimized for 12V and 19V bus rails (vs BSC076N04NDATMA1 (40V OptiMOS))
- Cross-brand equivalent available with same footprint (vs onsemi FDMS3660S)
설계 노트
The PG-TSDSON-8 (5x6 mm) package achieves its rated 30 W PD at TC by using the exposed drain pad as the primary thermal path. Per the Infineon datasheet, the device is characterized on a 40 mm x 40 mm x 1.5 mm FR4 PCB with 6 cm² (one layer, 70 um thick) copper area for drain connection - replicate this footprint in your design to achieve the rated thermal resistance. For higher dissipation, increase the drain copper area to 10+ cm² or add thermal vias to internal planes.
Place the BSZ100N03MSGATMA1 directly adjacent to the synchronous-rectifier position with the gate-drive loop (gate driver output -> MOSFET gate -> MOSFET source -> gate driver ground return) kept under 5 mm total loop length. Minimize the high dV/dt switching-node copper area to reduce EMI and gate-charge coupling. Use a kelvin source connection if available in the package variant, or route the gate-drive return separately from the power source return to avoid source-inductance-induced turn-on.
Do not exceed VGS absolute maximum of ±20 V (verify in datasheet Table 1); use a gate-drive voltage clamp or Zener protection if the driver can overshoot. The body diode has a limited reverse-recovery charge - in hard-switching topologies, ensure dead-time is < 50 ns to minimize body-diode conduction and prevent shoot-through. Verify avalanche energy rating during abnormal switching events (load-dump, output short); 100% avalanche testing per JEDEC provides margin but does not guarantee survival under all fault conditions.
For a 4-layer PCB stack-up (typical of server and datacom designs), place a continuous ground plane on layer 2 directly beneath the MOSFET to provide a low-impedance thermal path and to shield the gate-drive traces from the switching node. Stitch the drain copper to multiple vias connecting to internal power planes for improved thermal spreading. Avoid routing sensitive analog signals (feedback, current-sense) directly beneath the switching node to prevent capacitive coupling.
규정 준수 정보
Pb-free plating (tin terminal finish), halogen-free per IEC 61249-2-21. Qualified to JEDEC target-application standards. Not AEC-Q100 qualified; for automotive applications, select an Infineon OptiMOS part with explicit AEC-Q100 qualification.
