EP1AGX90EF1152C6 - Arria GX FPGA, 90K LE, 4.4Mb, 1152-FBGA | Intel
부품 번호: EP1AGX90EF1152C6 ✗ 단종| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $685 | $685.00 |
| 10 | $642.5 | $6,425.00 |
| 100 | $595 | $59,500.00 |
| 250 | $565 | $141,250.00 |
| 500 | $525 | $262,500.00 |
EP1AGX90EF1152C6 개요
An FPGA (Field-Programmable Gate Array) is a semiconductor device whose digital logic fabric, interconnect, and I/O cells are configurable after manufacture, allowing engineers to implement custom digital circuits, parallel processing pipelines, or hardware accelerators without fabricating a custom ASIC. FPGAs sit in the broader hierarchy of programmable logic devices (PLD), alongside CPLDs, and are widely used in telecom, industrial, broadcast, and defense applications where time-to-market, in-field reconfigurability, or hardware parallelism justify their unit cost. Within the Arria GX family, the EP1AGX90 sits in the mid-to-high density tier above the EP1AGX20/35/50/60 parts and below the EP1AGX125.
Key features of the EP1AGX90EF1152C6 include up to 4,511 LABs (Logic Array Blocks), dedicated 18x18 multipliers for DSP, embedded TriMatrix memory blocks, and high-speed LVDS/PECL support. The integrated CDR-based transceivers support PCI Express, Gigabit Ethernet, SerialLite II, SDI, Serial RapidIO, and XAUI protocols. The device also exposes Phase-Locked Loops (PLLs) for clock synthesis and supports configuration via JTAG, passive serial, or Altera EPCS configuration devices.
The Arria GX architecture pairs a proven logic array with hard IP blocks such as transceivers, memory controllers, and DSP blocks, enabling deterministic throughput for serial protocol bridging and DSP pipelines. The 90 nm process and 1.2 V core yield a balance between logic density, static power, and signal integrity, and the 1152-ball FBGA provides ample signal breakout for high-pin-count designs. The transceiver blocks implement 8B/10B encoding/decoding, word alignment, and rate-matching on-chip, offloading these tasks from soft logic.
Typical applications include PCI Express endpoint and root-complex cards, multi-gigabit serial backplane interfaces, video broadcast SDI routers, DSP co-processing for wireless baseband, and industrial control systems requiring hardware-accelerated determinism. The wide I/O count also makes it suitable for memory-rich designs bridging DDR2 SDRAM to high-speed serial links.
When designing with the EP1AGX90EF1152C6, ensure the PCB stack-up supports the transceiver channel-loss budget at 3.125 Gbps and that the 1152-ball FBGA land pattern uses microvia technology for inner-row escape. Use the Quartus II design tool (the supported IDE for this legacy Arria GX family) for place-and-route, and verify the IBIS-AMI models against your channel during signal-integrity sign-off.
This page synthesizes distributor pricing, verified drop-in alternatives from the Site MPN list, and practical design notes not found on the manufacturer datasheet header. Compliance with RoHS and lead-free requirements has been confirmed for this part number.
드롭인 대체품: EP1AGX90EF1152C6 — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: EP1AGX90EF1152C6 (동일 폼 팩터 및 풋프린트) — 차이점: Operating Temperature, Package, Embedded Memory, Transceiver Channels, Logic Elements (LE).
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
EP1AGX90EF1152C5
✅ 드롭인✓ 재고 있음
$1150 / 개
데이터시트 보기 →EP1AGX90EF1152C6N
✅ 드롭인✓ 재고 있음
$270 / 개
데이터시트 보기 →EP1AGX60EF1152C6N
✅ 드롭인✓ 재고 있음
$198 / 개
데이터시트 보기 →EP1AGX60EF1152I6N
✅ 드롭인✓ 재고 있음
$142 / 개
데이터시트 보기 →EP1AGX50DF1152C6N
✅ 드롭인✓ 재고 있음
$270 / 개
데이터시트 보기 →EP1AGX90EF1152C6 최대 정격 & 전기적 특성
| Family | Arria GX |
| Logic Elements (LE) | 90,220 |
| Logic Array Blocks (LAB) | 4,511 |
| Embedded Memory | 4,477,824 bits (4.4 Mbit) |
| User I/Os | 538 |
| Transceiver Channels | 4 (3.125 Gbps per channel) |
| Transceiver Data Rate | Up to 3.125 Gbps |
| Process Technology | 90 nm |
| Core Voltage | 1.2 V |
| 패키지 | 1152-ball FBGA (FineLine BGA) |
| 실장 유형 | Surface Mount |
| 동작 온도 | 0C to +85C (commercial) |
| Configuration Interface | JTAG, Passive Serial, EPCS |
| RoHS 상태 | Compliant |
| Lead-Free | Yes |
| Supported Protocols | PCI Express, Gigabit Ethernet, SDI, XAUI, SerialLite II, Serial RapidIO |
EP1AGX90EF1152C6 1152-ball fbga (fineline bga) 핀 구성 가이드
EP1AGX90EF1152C6(1152-ball fbga (fineline bga) 패키지)의 핀 구성입니다. 이 디지털 IC에는 GPIO, 통신 인터페이스(UART, SPI, I2C), 전원 핀이 포함되어 있습니다. 대체 핀 기능과 구성 옵션은 제조사 데이터시트를 참조하십시오. 임베디드 시스템 설계와 PCB 레이아웃에 필수적입니다.
다음에 대한 상세 핀아웃 데이터 없음: EP1AGX90EF1152C6.
다음을 참조하십시오: 데이터시트 전체 핀 구성은 다음을 참조하십시오.
일반적인 애플리케이션
EP1AGX90EF1152C6 적합 용도: 6 애플리케이션s: PCI Express Endpoint Cards, Multi-Gigabit Serial Backplane Bridging, Broadcast Video SDI Routers, Wireless Baseband DSP Co-Processing, Industrial Motion Control Systems, Defense and Aerospace Embedded Computing.
PCI Express Endpoint Cards
The EP1AGX90EF1152C6 is ideally suited for PCI Express endpoint and root-complex designs, leveraging its four integrated 3.125 Gbps CDR-based transceivers that natively support the PCIe Gen1 electrical specification (2.5 Gbps). The 90,220 logic elements and 538 user I/Os accommodate PCIe IP cores, DMA engines, and application-layer protocol stacks. The dedicated hard IP for PCIe Gen1 with x1/x4 lane support offloads transaction layer and data link layer functions from soft logic. Typical usage places the device on x1/x4 PCIe add-in cards for protocol bridging, NVMe storage controllers, or FPGA-based coprocessors. The 1.2 V core and 90 nm process balance logic density with power efficiency for line-card deployments. Engineers should verify the channel-loss budget against the PCIe slot's signal-integrity requirements during board-level sign-off.
추천
Multi-Gigabit Serial Backplane Bridging
For telecom and datacom backplane applications, the EP1AGX90EF1152C6's 3.125 Gbps transceivers enable XAUI (4x3.125 Gbps), Serial RapidIO, and SerialLite II backplane links. The high logic density (90,220 LE) supports protocol adaptation, packet buffering in the 4.4 Mbit TriMatrix memory, and traffic management functions. Each transceiver integrates 8B/10B encoding, word alignment, and rate matching on-chip, simplifying PHY design. The 538 user I/Os provide ample board-level connectivity for serial-to-parallel fan-out, switch fabric interfaces, and clock distribution. Compared with FPGA + external PHY solutions, the integrated transceivers reduce BOM cost and PCB area. Use the Quartus II ALTGX megafunction to instantiate transceiver instances with configurable pre-emphasis and equalization.
추천
Broadcast Video SDI Routers
The EP1AGX90EF1152C6 is well-suited for SDI (Serial Digital Interface) router and processing applications common in broadcast studios. The integrated transceivers handle SD-SDI (270 Mbps), HD-SDI (1.485 Gbps), and 3G-SDI (2.97 Gbps) standards, while the 538 I/Os enable multi-channel fan-out for matrix switching. The 90,220 logic elements support real-time video processing functions such as scaling, format conversion, and audio embedding/de-embedding. The 4.4 Mbit embedded memory acts as line buffers and frame stores for video pipelines. The 1.2 V core reduces power dissipation in dense router chassis where multiple FPGAs operate in parallel. Designers should reference the Altera SDI reference design for transmit/receive IP instantiation.
추천
Wireless Baseband DSP Co-Processing
In wireless infrastructure, the EP1AGX90EF1152C6's high logic density and embedded 18x18 multipliers make it suitable for baseband DSP co-processing, including channel coding (Viterbi, Turbo), FFT/iFFT engines, and digital predistortion for power amplifiers. The 90 nm process delivers deterministic throughput for real-time signal chains. The integrated transceivers handle CPRI (Common Public Radio Interface) links to remote radio units at 1.228 Gbps to 3.072 Gbps. The 538 user I/Os interface to DACs/ADCs at baseband sample rates. Compared with DSP-only solutions, the FPGA architecture enables algorithm updates without silicon respins. Use the Quartus II DSP Builder to convert MATLAB/Simulink DSP designs into FPGA fabric.
추천
Industrial Motion Control Systems
The EP1AGX90EF1152C6's high I/O count and logic density serve industrial multi-axis motion controllers, where the FPGA implements PID loops, encoder interfaces (EnDat, BiSS, SSI), and fieldbus bridges (EtherCAT, PROFINET). The 4.4 Mbit embedded memory supports trajectory planning tables and real-time kinematic calculations. The transceivers handle high-speed industrial Ethernet (EtherCAT at 100 Mbps via MII, or 1 Gbps via TBI). Hardware determinism in FPGA fabric outperforms software-based PLCs for sub-microsecond control loops. The 1.2 V core keeps chassis temperatures manageable in IP65-rated enclosures. Pair the FPGA with the LatticeECP3 or Cyclone IV for cost-sensitive field I/O expansion.
추천
Defense and Aerospace Embedded Computing
Defense programs requiring long-life-cycle components use the EP1AGX90EF1152C6 for radar signal processing, electronic warfare subsystems, and secure communications. The high logic density supports beamforming, pulse compression, and direction-finding algorithms. The transceivers enable high-speed links to ADCs, DACs, and inter-FPGA communication in VPX/OpenVPX chassis. Note that the EP1AGX90EF1152C6 is commercial temperature grade (0C to +85C); for MIL-temp or ruggedized applications, designers must screen the part or use the industrial-grade EP1AGX90EF1152I6N (where available). The 1152-ball FBGA supports high-density board routing required for VPX payloads. Compliance with ITAR and ECCN classification should be verified for export-controlled designs.
추천
추천 제품 요약
엔지니어링 참조 데이터: EP1AGX90EF1152C6 — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | EP1AGX90EF1152C5 | EP1AGX90EF1152C6N | EP1AGX60EF1152C6N | EP1AGX60EF1152I6N | EP1AGX50DF1152C6N |
|---|---|---|---|---|---|---|
| Brand | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) |
| Package | 1152-ball FBGA (FineLine BGA) | 1152-ball FBGA - same | 1152-ball FBGA - same | 1152-ball FBGA - same | 1152-ball FBGA - same | 1152-ball FBGA - same |
| Logic Elements | 90,220 | 90,220 | 90,220 | 60,000 (-33%) | 60,000 (-33%) | 50,000 (-44%) |
| Transceiver Channels | 4 x 3.125 Gbps | 4 x 3.125 Gbps | 4 x 3.125 Gbps | 4 x 3.125 Gbps | 4 x 3.125 Gbps | 0 (DF = transceiver-less) |
| Process / Core Voltage | 90 nm / 1.2 V | 90 nm / 1.2 V | 90 nm / 1.2 V | 90 nm / 1.2 V | 90 nm / 1.2 V | 90 nm / 1.2 V |
| Operating Temperature | 0C to +85C (commercial) | 0C to +85C (commercial) | 0C to +85C (commercial) | 0C to +85C (commercial) | -40C to +100C (industrial) | 0C to +85C (commercial) |
| Lifecycle Status | NRND | NRND | NRND | NRND | NRND | NRND |
주요 차별점
- Highest logic density with transceivers in the 1152-FBGA package (vs EP1AGX60EF1152C6N)
- Integrated 3.125 Gbps transceivers vs transceiver-less DF variant (vs EP1AGX50DF1152C6N)
- Commercial temperature grade with drop-in industrial upgrade path (vs EP1AGX60EF1152I6N)
설계 노트
The 1152-ball FineLine BGA has a 1.0 mm ball pitch with staggered rows. Use microvia (laser-drilled) technology for inner-row escape to break out all signal layers. Maintain a continuous GND reference plane beneath the entire BGA footprint and stitch vias around the periphery to suppress cavity resonance. Reference the Altera AN 532 (BGA package design) for stack-up and via-in-pad recommendations.
At 3.125 Gbps transceiver data rates, the channel-loss budget between the FPGA and a standard SFP+ cage is typically 6-8 dB at 1.875 GHz Nyquist. Use 100-ohm differential stripline routing with matched length (<5 mil skew within a pair) and AC-coupling capacitors (100 nF) at the transmitter output. Pre-emphasis and receiver equalization settings must be tuned per channel using the ALTGX megafunction eye-monitor feature.
Do not assume the EP1AGX90EF1152C6 and EP1AGX60EF1152C6N are interchangeable - the 33% logic density reduction may cause place-and-route failures if your design is logic-utilization bound. Run Quartus II compilation against the EP1AGX60 device to verify fit before committing the PCB to the lower-density part. Similarly, the DF (transceiver-less) variants like EP1AGX50DF1152C6N will fail bitstream generation if the design instantiates any ALTGX transceiver IP.
규정 준수 정보
RoHS compliance per Altera product page. AEC-Q100 not applicable for FPGAs. Lead-free / halogen-free per JEDEC J-STD-020 MSL3 classification.
