EP1AGX90EF1152C6 - Arria GX FPGA, 90K LE, 4.4Mb, 1152-FBGA | Intel
MPN: EP1AGX90EF1152C6 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $685 | $685.00 |
| 10 | $642.5 | $6,425.00 |
| 100 | $595 | $59,500.00 |
| 250 | $565 | $141,250.00 |
| 500 | $525 | $262,500.00 |
Drop-in alternatives for EP1AGX90EF1152C6 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP1AGX90EF1152C5
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$1150 / Unit
View Datasheet →EP1AGX90EF1152C6N
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View Datasheet →EP1AGX60EF1152C6N
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View Datasheet →EP1AGX60EF1152I6N
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View Datasheet →EP1AGX50DF1152C6N
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$270 / Unit
View Datasheet →EP1AGX90EF1152C6 Maximum Ratings & Electrical Characteristics
| Family | Arria GX |
| Logic Elements (LE) | 90,220 |
| Logic Array Blocks (LAB) | 4,511 |
| Embedded Memory | 4,477,824 bits (4.4 Mbit) |
| User I/Os | 538 |
| Transceiver Channels | 4 (3.125 Gbps per channel) |
| Transceiver Data Rate | Up to 3.125 Gbps |
| Process Technology | 90 nm |
| Core Voltage | 1.2 V |
| Package | 1152-ball FBGA (FineLine BGA) |
| Mounting Type | Surface Mount |
| Operating Temperature | 0C to +85C (commercial) |
| Configuration Interface | JTAG, Passive Serial, EPCS |
| RoHS Status | Compliant |
| Lead-Free | Yes |
| Supported Protocols | PCI Express, Gigabit Ethernet, SDI, XAUI, SerialLite II, Serial RapidIO |
EP1AGX90EF1152C6 1152-ball fbga (fineline bga) Pin Configuration Guide
Complete pinout information for EP1AGX90EF1152C6 (1152-ball fbga (fineline bga) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP1AGX90EF1152C6.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EP1AGX90EF1152C6 is suitable for 6 applications: PCI Express Endpoint Cards, Multi-Gigabit Serial Backplane Bridging, Broadcast Video SDI Routers, Wireless Baseband DSP Co-Processing, Industrial Motion Control Systems, Defense and Aerospace Embedded Computing.
PCI Express Endpoint Cards
The EP1AGX90EF1152C6 is ideally suited for PCI Express endpoint and root-complex designs, leveraging its four integrated 3.125 Gbps CDR-based transceivers that natively support the PCIe Gen1 electrical specification (2.5 Gbps). The 90,220 logic elements and 538 user I/Os accommodate PCIe IP cores, DMA engines, and application-layer protocol stacks. The dedicated hard IP for PCIe Gen1 with x1/x4 lane support offloads transaction layer and data link layer functions from soft logic. Typical usage places the device on x1/x4 PCIe add-in cards for protocol bridging, NVMe storage controllers, or FPGA-based coprocessors. The 1.2 V core and 90 nm process balance logic density with power efficiency for line-card deployments. Engineers should verify the channel-loss budget against the PCIe slot's signal-integrity requirements during board-level sign-off.
Recommended
Multi-Gigabit Serial Backplane Bridging
For telecom and datacom backplane applications, the EP1AGX90EF1152C6's 3.125 Gbps transceivers enable XAUI (4x3.125 Gbps), Serial RapidIO, and SerialLite II backplane links. The high logic density (90,220 LE) supports protocol adaptation, packet buffering in the 4.4 Mbit TriMatrix memory, and traffic management functions. Each transceiver integrates 8B/10B encoding, word alignment, and rate matching on-chip, simplifying PHY design. The 538 user I/Os provide ample board-level connectivity for serial-to-parallel fan-out, switch fabric interfaces, and clock distribution. Compared with FPGA + external PHY solutions, the integrated transceivers reduce BOM cost and PCB area. Use the Quartus II ALTGX megafunction to instantiate transceiver instances with configurable pre-emphasis and equalization.
Recommended
Broadcast Video SDI Routers
The EP1AGX90EF1152C6 is well-suited for SDI (Serial Digital Interface) router and processing applications common in broadcast studios. The integrated transceivers handle SD-SDI (270 Mbps), HD-SDI (1.485 Gbps), and 3G-SDI (2.97 Gbps) standards, while the 538 I/Os enable multi-channel fan-out for matrix switching. The 90,220 logic elements support real-time video processing functions such as scaling, format conversion, and audio embedding/de-embedding. The 4.4 Mbit embedded memory acts as line buffers and frame stores for video pipelines. The 1.2 V core reduces power dissipation in dense router chassis where multiple FPGAs operate in parallel. Designers should reference the Altera SDI reference design for transmit/receive IP instantiation.
Recommended
Wireless Baseband DSP Co-Processing
In wireless infrastructure, the EP1AGX90EF1152C6's high logic density and embedded 18x18 multipliers make it suitable for baseband DSP co-processing, including channel coding (Viterbi, Turbo), FFT/iFFT engines, and digital predistortion for power amplifiers. The 90 nm process delivers deterministic throughput for real-time signal chains. The integrated transceivers handle CPRI (Common Public Radio Interface) links to remote radio units at 1.228 Gbps to 3.072 Gbps. The 538 user I/Os interface to DACs/ADCs at baseband sample rates. Compared with DSP-only solutions, the FPGA architecture enables algorithm updates without silicon respins. Use the Quartus II DSP Builder to convert MATLAB/Simulink DSP designs into FPGA fabric.
Recommended
Industrial Motion Control Systems
The EP1AGX90EF1152C6's high I/O count and logic density serve industrial multi-axis motion controllers, where the FPGA implements PID loops, encoder interfaces (EnDat, BiSS, SSI), and fieldbus bridges (EtherCAT, PROFINET). The 4.4 Mbit embedded memory supports trajectory planning tables and real-time kinematic calculations. The transceivers handle high-speed industrial Ethernet (EtherCAT at 100 Mbps via MII, or 1 Gbps via TBI). Hardware determinism in FPGA fabric outperforms software-based PLCs for sub-microsecond control loops. The 1.2 V core keeps chassis temperatures manageable in IP65-rated enclosures. Pair the FPGA with the LatticeECP3 or Cyclone IV for cost-sensitive field I/O expansion.
Recommended
Defense and Aerospace Embedded Computing
Defense programs requiring long-life-cycle components use the EP1AGX90EF1152C6 for radar signal processing, electronic warfare subsystems, and secure communications. The high logic density supports beamforming, pulse compression, and direction-finding algorithms. The transceivers enable high-speed links to ADCs, DACs, and inter-FPGA communication in VPX/OpenVPX chassis. Note that the EP1AGX90EF1152C6 is commercial temperature grade (0C to +85C); for MIL-temp or ruggedized applications, designers must screen the part or use the industrial-grade EP1AGX90EF1152I6N (where available). The 1152-ball FBGA supports high-density board routing required for VPX payloads. Compliance with ITAR and ECCN classification should be verified for export-controlled designs.
Recommended
Recommended Products Summary
Engineering reference data for EP1AGX90EF1152C6 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP1AGX90EF1152C5 | EP1AGX90EF1152C6N | EP1AGX60EF1152C6N | EP1AGX60EF1152I6N | EP1AGX50DF1152C6N |
|---|---|---|---|---|---|---|
| Brand | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) |
| Package | 1152-ball FBGA (FineLine BGA) | 1152-ball FBGA - same | 1152-ball FBGA - same | 1152-ball FBGA - same | 1152-ball FBGA - same | 1152-ball FBGA - same |
| Logic Elements | 90,220 | 90,220 | 90,220 | 60,000 (-33%) | 60,000 (-33%) | 50,000 (-44%) |
| Embedded Memory | 4,477,824 bits (4.4 Mbit) | 4,477,824 bits | 4,477,824 bits | [DATA_NEEDED: AGX60 memory] | [DATA_NEEDED: AGX60 memory] | [DATA_NEEDED: AGX50 memory] |
| Transceiver Channels | 4 x 3.125 Gbps | 4 x 3.125 Gbps | 4 x 3.125 Gbps | 4 x 3.125 Gbps | 4 x 3.125 Gbps | 0 (DF = transceiver-less) |
| User I/Os | 538 | 538 | 538 | [DATA_NEEDED: AGX60 I/O count] | [DATA_NEEDED: AGX60 I/O count] | [DATA_NEEDED: AGX50 I/O count] |
| Process / Core Voltage | 90 nm / 1.2 V | 90 nm / 1.2 V | 90 nm / 1.2 V | 90 nm / 1.2 V | 90 nm / 1.2 V | 90 nm / 1.2 V |
| Operating Temperature | 0C to +85C (commercial) | 0C to +85C (commercial) | 0C to +85C (commercial) | 0C to +85C (commercial) | -40C to +100C (industrial) | 0C to +85C (commercial) |
| Lifecycle Status | NRND | NRND | NRND | NRND | NRND | NRND |
| Unit Price (1 qty, USD) | $685 | [DATA_NEEDED: C5 price] | [DATA_NEEDED: C6N price] | [DATA_NEEDED: AGX60 price] | [DATA_NEEDED: AGX60I price] | [DATA_NEEDED: AGX50 price] |
Key Differentiators
- Highest logic density with transceivers in the 1152-FBGA package (vs EP1AGX60EF1152C6N)
- Integrated 3.125 Gbps transceivers vs transceiver-less DF variant (vs EP1AGX50DF1152C6N)
- Commercial temperature grade with drop-in industrial upgrade path (vs EP1AGX60EF1152I6N)
Design Notes
The 1152-ball FineLine BGA has a 1.0 mm ball pitch with staggered rows. Use microvia (laser-drilled) technology for inner-row escape to break out all signal layers. Maintain a continuous GND reference plane beneath the entire BGA footprint and stitch vias around the periphery to suppress cavity resonance. Reference the Altera AN 532 (BGA package design) for stack-up and via-in-pad recommendations.
At 3.125 Gbps transceiver data rates, the channel-loss budget between the FPGA and a standard SFP+ cage is typically 6-8 dB at 1.875 GHz Nyquist. Use 100-ohm differential stripline routing with matched length (<5 mil skew within a pair) and AC-coupling capacitors (100 nF) at the transmitter output. Pre-emphasis and receiver equalization settings must be tuned per channel using the ALTGX megafunction eye-monitor feature.
Do not assume the EP1AGX90EF1152C6 and EP1AGX60EF1152C6N are interchangeable - the 33% logic density reduction may cause place-and-route failures if your design is logic-utilization bound. Run Quartus II compilation against the EP1AGX60 device to verify fit before committing the PCB to the lower-density part. Similarly, the DF (transceiver-less) variants like EP1AGX50DF1152C6N will fail bitstream generation if the design instantiates any ALTGX transceiver IP.
Compliance Information
RoHS compliance per Altera product page. AEC-Q100 not applicable for FPGAs. Lead-free / halogen-free per JEDEC J-STD-020 MSL3 classification.
