EP1AGX60EF1152I6N - Arria GX 60 FPGA, 60K LE, 1152-BGA | Intel / Altera
MPN: EP1AGX60EF1152I6N ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $285 | $285.00 |
| 10 | $245 | $2,450.00 |
| 100 | $198 | $19,800.00 |
| 500 | $165 | $82,500.00 |
| 1,000 | $142 | $142,000.00 |
Drop-in alternatives for EP1AGX60EF1152I6N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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EP1AGX60EF1152C6N
✅ Drop-In✓ In Stock
$198 / Unit
View Datasheet →EP1AGX60DF1152I6N
✅ Drop-In📋 Reference alternative (not in catalog)
EP1AGX60EF1152I6N Maximum Ratings & Electrical Characteristics
| Series | Arria GX |
| Family | Arria GX FPGA |
| Logic Elements (LE) | 60,100 |
| Embedded Memory | 2,528,640 bits (≈2.4 Mbit) |
| LABs / CLBs | 3,005 |
| Total RAM Bits | 2,528,640 |
| User I/O Count | 514 |
| Transceiver Channels | 12 (3.125 Gbps, embedded CDR/SERDES) |
| 18 × 18 Hardware Multipliers | 252 |
| PLLs | 4 (one per quadrant) plus transceiver PLLs |
| Package | 1152-BBGA (FBGA-1152, 35 × 35 mm, 1.0 mm pitch) |
| Mounting Type | Surface Mount (BGA) |
| Operating Temperature | -40 °C to +100 °C (Industrial, suffix I) |
| Speed Grade | 6 |
| Process Node | 90 nm |
| Hard IP | PCI Express ×1/×4, Gigabit Ethernet MAC, 8B/10B encoder/decoder |
| Memory Interfaces | DDR, DDR2, QDRII, RLDRAM (external memory controller) |
| RoHS Status | Compliant (per distributor listing) |
| MSL Level | 3 (per JEDEC J-STD-020) |
EP1AGX60EF1152I6N 1152-bbga (fbga-1152, 35 × 35 mm, 1.0 mm pitch) Pin Configuration Guide
Complete pinout information for EP1AGX60EF1152I6N (1152-bbga (fbga-1152, 35 × 35 mm, 1.0 mm pitch) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP1AGX60EF1152I6N.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EP1AGX60EF1152I6N is suitable for 7 applications: PCI Express Endpoint Card, Gigabit Ethernet Aggregation / Network Interface, Broadcast SDI / HD-SDI Video Router, Serial RapidIO Switch / Endpoint, XAUI / 10 GbE Backplane Aggregation, Industrial Machine Vision / Camera Link, Test & Measurement Backplane.
PCI Express Endpoint Card
The EP1AGX60EF1152I6N's 3.125 Gbps transceivers and embedded PCIe hard IP ×1/×4 endpoint make it ideal for half-height PCIe cards. Placed on a 4-lane PCIe slot, the FPGA offloads DMA engines and custom protocols into the 60,100 logic elements while the dedicated PCIe block handles transaction/data-link layers at 2.5 Gbps per lane, freeing fabric for application logic. Industrial temp grade suits indoor server and workstation deployments where extended-temperature hardening is required.
Recommended
Gigabit Ethernet Aggregation / Network Interface
With 12 transceivers capable of 3.125 Gbps and embedded Gigabit Ethernet MAC hard IP, the EP1AGX60EF1152I6N fits multi-port GbE aggregation cards. Designers wire four SFP cages to four transceiver channels running serial Gigabit Ethernet, implement an aggregation switch in fabric, and expose the result through PCIe to a host CPU. The 514 user I/O and external DDR2 interface support buffer memory for line-rate packet processing. Industrial temp supports carrier-grade deployment in controlled environments.
Recommended
Broadcast SDI / HD-SDI Video Router
The EP1AGX60EF1152I6N's transceivers natively clock 270 Mbps SDI, 1.485 Gbps HD-SDI, and 2.97 Gbps 3G-SDI rates that fall within the 3.125 Gbps capability. Routing fabric in 60K LE handles large cross-point matrices while dedicated transceivers provide the serializer/deserializer function for SDI. The 252 hardware 18x18 multipliers assist with video scaling and color-space conversion. Industrial temp covers 24/7 broadcast infrastructure requirements.
Recommended
Serial RapidIO Switch / Endpoint
The 3.125 Gbps transceivers support Serial RapidIO (SRIO) physical layer at 1x and 4x lane widths with 8B/10B coding. The EP1AGX60EF1152I6N acts as a logical layer switch endpoint in baseband DSP cards for wireless infrastructure, where it bridges SRIO to host processors. With 60K logic elements, the device supports 4x SRIO port plus fabric logic for DMA, message passing, and shared-memory transport. Industrial temp supports outdoor cell-site equipment.
Recommended
XAUI / 10 GbE Backplane Aggregation
XAUI (10 Gbps Ethernet over four 3.125 Gbps lanes) maps directly onto the EP1AGX60EF1152I6N transceiver channels. Four transceivers combine to form one XAUI lane, supporting up to three independent 10 GbE ports. The 60,100 LE fabric is large enough for 10 GbE MAC plus classification/queueing logic, and the external DDR2 controller provides 36-bit wide buffer memory at 333 MHz data rate. Industrial temp suits telecom central-office installations.
Recommended
Industrial Machine Vision / Camera Link
The 514 user I/O and 252 hardware multipliers make the EP1AGX60EF1152I6N suitable for Camera Link base/medium/full/extended configurations. Designers pair transceivers with external LVDS pairs (via the 514 I/O) to receive Camera Link data at up to 6.8 Gbps, then process frames in 60K logic elements using the on-chip multipliers for Bayer demosaic and color correction. Industrial temp supports factory-floor deployment in vision-guided robotics cells.
Recommended
Test & Measurement Backplane
The 12 transceiver channels and 514 I/O make the EP1AGX60EF1152I6N an ideal protocol-aware backplane for ATE systems. Logic implements pattern generators and protocol analyzers (PCIe Gen1, GbE, SRIO, XAUI) on the same device, switching between instruments via soft logic. Industrial temp allows use in temperature-controlled production test cells. The DDR2 controller stores captured waveforms for post-processing in the host.
Recommended
Recommended Products Summary
Engineering reference data for EP1AGX60EF1152I6N — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP1AGX60EF1152C6N | EP1AGX60DF1152I6N |
|---|---|---|---|
| Brand | Intel (legacy Altera) | Intel (legacy Altera) | Intel (legacy Altera) |
| Package | 1152-BBGA (FBGA-1152, 35×35 mm) | 1152-BBGA (FBGA-1152, 35×35 mm) - same | 1152-BBGA (FBGA-1152) - same |
| Logic Elements | 60,100 | 60,100 | 60,100 |
| Transceiver Channels | 12 × 3.125 Gbps | 12 × 3.125 Gbps | 8 × 3.125 Gbps |
| User I/O | 514 | 514 | 514 |
| Embedded Memory (bits) | 2,528,640 | 2,528,640 | 2,528,640 |
| Temperature Grade | Industrial -40 to +100 C | Commercial 0 to +85 C | Industrial -40 to +100 C |
| Speed Grade | 6 | 6 | 6 |
| Lifecycle Status | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Industrial temperature grade availability in same 1152-BBGA footprint (vs EP1AGX60EF1152C6N)
- Full 12-channel 3.125 Gbps transceiver array (vs EP1AGX60DF1152I6N)
- Embedded hard IP for PCIe, GbE and 8B/10B coding (vs Stratix-based predecessors (e.g. EP1S80B956C6))
Design Notes
The FBGA-1152 package has a thermal resistance theta-JA of approximately 8-10 °C/W with a 4-layer JEDEC JESD51 test board, requiring designers to budget power dissipation. Estimated: at 8 W total power (60% utilization with active transceivers), the junction temperature rises 64-80 °C above ambient. Industrial-temperature operation at +100 °C ambient requires that the 8 W figure be derated to keep Tj below +125 °C. Use the Altera PowerPlay Early Power Estimator spreadsheet for design-specific analysis before PCB layout commitment.
The 1152-BBGA package requires a 35 × 35 mm PCB land pattern with 1.0 mm ball pitch. Use microvia or sub-100 µm laser-drilled vias in-pad to route the inner-row balls. Implement a 12-layer stack-up with continuous GND and PWR planes adjacent to the BGA break-out layer; transceiver channels require 100 Ω differential impedance with 7-9 mil trace width and intra-pair skew below 5 ps. Power decoupling requires 0402/0201 ceramic capacitors within 100 mils of each VCC/VCCINT/VCCA ball pair.
Place transceiver channels on the package edges closest to the SMA/edge connector I/O to minimize PCB routing. Keep the 3.125 Gbps lanes length-matched within 150 mil pair-to-pair and maintain at least 3W spacing from other high-speed signals. Reference the Altera AN 465 application note for Arria GX transceiver PCB layout, which specifies the via anti-pad geometry and AC-coupling capacitor placement. JTAG and configuration pins (TCK, TMS, TDI, TDO, nCONFIG, nSTATUS, CONF_DONE) require 4.7 kΩ pull-ups per the device handbook.
All 12 transceiver channels require external AC-coupling capacitors (typically 100 nF X7R 0402) on each TX/RX pair. The Arria GX CDR is calibrated at power-up via the Quartus II transceiver toolkit; designers must supply a stable reference clock to the dedicated refclk pins with jitter below 100 fs RMS for 3.125 Gbps operation. Pre-emphasis and equalization settings are programmable through the ALTGX megafunction; default settings provide 6 dB pre-emphasis suitable for backplanes up to 30 cm.
Do not assume I/O standards across banks - each I/O bank has independent VCCIO supply and supports LVDS, LVTTL, LVCMOS, SSTL-2, SSTL-18, HSTL, and PCI/PCI-X signaling. The CONF_DONE pin must be pulled high before configuration completes, or the device enters an undefined state. Configuration via fast passive parallel (FPP) requires a 16-bit data bus and clock; using an EPCS16 serial configuration device is recommended for cost-sensitive designs but requires fewer pins.
Compliance Information
RoHS-compliant per DigiKey product listing 1629504. Not AEC-Q100 qualified (industrial, not automotive grade). Halogen-free status not explicitly listed by distributor; consult Intel product declaration.
