EP1S20F672C7N - Stratix 18460-Cell FPGA, 672-FBGA | Intel | Embedded
부품 번호: EP1S20F672C7N ✗ 단종| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $185 | $185.00 |
| 10 | $162.5 | $1,625.00 |
| 100 | $138.75 | $13,875.00 |
| 500 | $121.4 | $60,700.00 |
| 1,000 | $109.2 | $109,200.00 |
EP1S20F672C7N 개요
An FPGA (Field Programmable Gate Array) is a programmable logic device that allows hardware designers to implement custom digital circuits after PCB fabrication. The EP1S20F672C7N sits in the Stratix hierarchy as Stratix -> high-density FPGA -> programmable logic -> semiconductor. It is a member of Intel's (formerly Altera's) first-generation Stratix family, introduced in 2002 as a high-performance, embedded-memory-rich alternative to ASICs. Compared with subsequent Stratix II/III/IV/V families, this first-generation part uses 130nm process technology rather than 90/65/40/28nm, but retains pin-out, JTAG, and Quartus II tool compatibility that keeps it in service for legacy designs.
Key features include 18,460 logic elements (LEs), 1,669,248 RAM bits organized into 426 Kbits of TriMatrix memory (three block RAM sizes), 56 DSP blocks implemented as dedicated 18x18 multipliers, and 586 maximum user I/Os. The device also integrates up to 12 phase-locked loops (PLLs) and supports configuration via passive serial (PS), passive parallel synchronous (PPS), fast passive parallel (FPP), and JTAG modes. The 672-FBGA package offers a compact, high-density ball grid that enables high pin count in a moderate footprint.
Typical applications include telecommunications line cards, industrial motor control, military and aerospace signal processing, and embedded DSP pre-processing. The dedicated 18x18 multipliers and high I/O count also make this part suitable for custom PCI bridge logic, mid-range video processing, and software-defined radio front-end buffering. The wide I/O voltage range (1.5V core, 3.3V/2.5V/1.8V I/O capability via banked VCCIO rails) allows bridging between multiple logic standards on a single die.
When designing with this device, note that the EP1S20F672C7N is in the Stratix EOL/EOS phase and the part is now sourced primarily through the secondary/excess market and franchised distributors carrying legacy inventory. Designers should plan for long-term supply continuity using PCN-aware sourcing, validate thermal management for the 672-ball package (which presents a non-trivial theta-JA of approximately 11-13 C/W on a 4-layer JEDEC JESD51 test board), and confirm Quartus II software version compatibility (this part is not supported in Quartus Prime). The lead-free 672-FBGA requires lead-free reflow profile per JEDEC J-STD-020.
드롭인 대체품: EP1S20F672C7N — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: EP1S20F672C7N (동일 폼 팩터 및 풋프린트) — 차이점: Package, Operating Temperature, Speed Grade, Family, Embedded Memory Bits.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
EP1S20F672C7
✅ 드롭인 ⚠️ 사양 미검증✓ 재고 있음
$195 / 개
데이터시트 보기 →EP1S20F672C6N
✅ 드롭인✓ 재고 있음
$68.9 / 개
데이터시트 보기 →EP1S20F672C6
✅ 드롭인 ⚠️ 사양 미검증✓ 재고 있음
$470 / 개
데이터시트 보기 →EP1S20F672C7N 최대 정격 & 전기적 특성
| Series | Stratix (first generation) |
| Family | Stratix |
| Logic Elements (LEs) | 18,460 |
| Logic Cells | 18,460 |
| Configurable Logic Blocks (CLBs) | 2,132 |
| Embedded Memory (TriMatrix) | 1,669,248 bits (426 Kbit total) |
| DSP Blocks | 56 (dedicated 18x18 multipliers) |
| Maximum User I/O | 586 |
| PLLs | Up to 12 |
| Maximum Operating Frequency | 420.17 MHz |
| Core Voltage | 1.5 V |
| Process Technology | 130 nm CMOS |
| 패키지 | 672-FBGA (FineLine BGA) |
| Package Body Size | 35 mm x 35 mm |
| Ball Pitch | 1.27 mm |
| 동작 온도 | 0°C to +85°C (commercial) |
| Speed Grade | C7 (-7) |
| 실장 유형 | Surface Mount |
| Lead-Free / RoHS | Yes (lead-free finish, RoHS compliant) |
| Configuration Modes | PS, PPS, FPP, JTAG |
EP1S20F672C7N 35 mm x 35 mm 핀 구성 가이드
EP1S20F672C7N(35 mm x 35 mm 패키지)의 핀 구성입니다. 이 디지털 IC에는 GPIO, 통신 인터페이스(UART, SPI, I2C), 전원 핀이 포함되어 있습니다. 대체 핀 기능과 구성 옵션은 제조사 데이터시트를 참조하십시오. 임베디드 시스템 설계와 PCB 레이아웃에 필수적입니다.
다음에 대한 상세 핀아웃 데이터 없음: EP1S20F672C7N.
다음을 참조하십시오: 데이터시트 전체 핀 구성은 다음을 참조하십시오.
일반적인 애플리케이션
EP1S20F672C7N 적합 용도: 6 애플리케이션s: Telecommunications Line Card Glue Logic, Industrial Motor Control and Drive, Legacy Software-Defined Radio Front-End Buffer, Military/Aerospace Signal Processing, Embedded DSP Pre-Processing, Custom PCI / Bus Bridge Logic.
Telecommunications Line Card Glue Logic
The EP1S20F672C7N's 18,460 logic elements, 586 user I/Os, and 56 dedicated 18x18 multipliers suit it for telecom line-card glue logic that bridges network processors, SERDES, and backplane PHYs. The 1.5V core with multi-voltage I/O banks (3.3V/2.5V/1.8V/1.5V via VCCIO) allows direct connection to LVTTL, LVCMOS, SSTL, and HSTL interfaces common in telecom backplanes. With 420 MHz internal performance and up to 12 PLLs, the device can implement rate-matching FIFOs, UTOPIA/SerDes adapters, and custom packet-classification engines. The 1,669,248-bit TriMatrix memory (426 Kbit total) is sufficient for typical 4-8 KB packet buffers per port.
추천
Industrial Motor Control and Drive
The EP1S20F672C7N's 56 dedicated 18x18 hardware multipliers combined with 18,460 logic elements make it well suited for FOC (field-oriented control), space-vector PWM, and encoder-feedback processing in industrial drives up to ~50 kW. The device's 1.27mm-pitch 672-FBGA package is rated for industrial operating temperatures when paired with proper thermal management. The 426 Kbit TriMatrix memory holds Q-axis/d-axis reference frames and pre-computed sine/cosine LUTs without external SRAM. The 12 PLLs allow multiple PWM-aligned clock domains for inverter, ADC, and resolver interfaces. Designers typically pair the FPGA with external 16-bit ADCs and gate drivers, using the 586 I/Os to fan out signals.
추천
Legacy Software-Defined Radio Front-End Buffer
The EP1S20F672C7N's combination of 18,460 LEs, 56 18x18 multipliers, and 1,669,248 bits of memory targets legacy SDR front-end DSP stages such as digital down-conversion (DDC), FIR filtering, and resampling. At 420 MHz, each 18x18 multiplier supports FIR tap rates up to ~420 MSPS, and 56 multipliers allow 8-tap FIR at 56/8 = 7 channels simultaneously, or a single 56-tap channel. The TriMatrix memory (M512/M4K/MRAM blocks) supports sample buffers and NCO phase accumulators. Multi-bank I/O lets the device accept LVDS data from a wideband ADC while outputting LVTTL/LVCMOS to a downstream DSP processor.
추천
Military/Aerospace Signal Processing
The EP1S20F672C7N's lead-free 672-FBGA package, 130nm CMOS architecture, and 18,460 logic elements are deployed in legacy military and aerospace signal-processing subsystems where bitstream maturity and -7 speed grade are validated for the program. The device's 56 hardware multipliers support FFT/iFFT and channelization operations common in EW (electronic warfare) and SIGINT payloads. Memory-rich TriMatrix architecture simplifies sample-rate conversion, while 586 I/Os accommodate parallel ADC and DAC interfaces typical of MIL-STD-1553 and custom sensor fabrics. Designers must verify long-term supply through franchised distributors and program life-of-buy arrangements.
추천
Embedded DSP Pre-Processing
The EP1S20F672C7N serves as a pre-processor in imaging, video, and medical imaging pipelines where 56 dedicated 18x18 multipliers and 1,669,248 bits of embedded memory accelerate FIR filters, motion estimation, and color-space conversion before handing data to a host CPU. The -7 speed grade sustains 420 MHz fabric performance, allowing real-time processing of standard-definition video at 60 Hz. Multi-bank I/O supports concurrent connection to image sensors (LVDS) and DDR memory controllers (SSTL). Pin-compatible lower-cost variants such as the EP1S20F672C6N allow program-cost optimization once design timing is closed at -6 grade.
추천
Custom PCI / Bus Bridge Logic
The EP1S20F672C7N's 586 user I/Os and 12 PLLs make it well suited for custom PCI, PCI-X, and proprietary parallel-bus bridges that require multiple clock domains and protocol adaptation. The device can implement bus arbitration, scatter-gather DMA controllers, and protocol-translation state machines. The 426 Kbit TriMatrix memory supports descriptor rings and small FIFOs for short-packet workloads. Lead-free 672-FBGA packaging and 0-85°C commercial temperature rating suit industrial embedded SBC (single-board computer) designs where the FPGA handles interface translation between a host processor and legacy I/O.
추천
추천 제품 요약
엔지니어링 참조 데이터: EP1S20F672C7N — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | EP1S20F672C7 | EP1S20F672C6N | EP1S20F672C6 |
|---|---|---|---|---|
| Package | 672-FBGA (35x35mm, 1.27mm pitch) | 672-FBGA (35x35mm, 1.27mm pitch) - same | 672-FBGA (35x35mm, 1.27mm pitch) - same | 672-FBGA (35x35mm, 1.27mm pitch) - same |
| Brand | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) |
| Speed Grade | C7 (-7) | C7 (-7) | C6 (-6, ~15% slower) | C6 (-6, ~15% slower) |
| Lead-Free Finish | Yes (RoHS, 'N' suffix) | No (SnPb) | Yes (RoHS) | No (SnPb) |
| Logic Elements | 18,460 | 18,460 | 18,460 | 18,460 |
| Embedded Memory | 1,669,248 bits (426 Kbit) | 1,669,248 bits (426 Kbit) | 1,669,248 bits (426 Kbit) | 1,669,248 bits (426 Kbit) |
| DSP / 18x18 Multipliers | 56 | 56 | 56 | 56 |
| Maximum User I/O | 586 | 586 | 586 | 586 |
| Core Voltage | 1.5 V | 1.5 V | 1.5 V | 1.5 V |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete |
주요 차별점
- Lead-free RoHS-compliant finish with original -7 speed grade (vs EP1S20F672C7)
- Faster speed grade than -6 alternatives (vs EP1S20F672C6N)
- Smaller and lower-pin-count than 780-FBGA siblings (vs EP1S20F780C7N)
설계 노트
The 672-FBGA package's thermal performance is dominated by PCB copper area and thermal via count under the die. Estimated: with 1oz copper on a 4-layer JEDEC JESD51 board and a typical 5x5 thermal via array under the package, theta-JA is approximately 11-13 C/W. At 2W dissipation this yields a 22-26°C junction temperature rise above ambient; at 5W, 55-65°C. Active cooling is recommended for sustained >3W operation. Boundary-scan and JTAG-only designs with low toggle rates typically run <1W.
Place 1.5V VCCINT decoupling capacitors (0.1µF X7R) within 50 mils of every dedicated VCCINT ball, with bulk 10µF X5R capacitors distributed across the FPGA footprint. VCCIO banks each require their own decoupling network sized for the I/O toggle rate - LVDS banks need a ferrite bead plus 0.1µF + 10µF, while LVTTL banks typically need only 0.1µF + 4.7µF. VCCA_PLL pins must connect to a quiet 1.5V rail through a ferrite bead per the Stratix Handbook recommendation.
Do not attempt to synthesize a new design for this part in Quartus Prime - first-generation Stratix is supported only by Quartus II 13.0sp1 and earlier. Configuration bitstreams are incompatible with Quartus Prime. When designing for lead-free reflow, ensure the PCB profile follows JEDEC J-STD-020 with a peak body temperature of 245°C for the SnAgCu ball finish. Do not mix EP1S20F672C7 (SnPb) and EP1S20F672C7N (lead-free) on the same board, as bi-metallic solder joints are unreliable.
규정 준수 정보
RoHS compliance inferred from the 'N' suffix in the MPN (Altera/Intel convention for lead-free finish). REACH, halogen-free, and conflict-minerals status were not present in the verified web data and are marked 'unknown'. AEC-Q100 is not applicable because this is a commercial-grade FPGA in the C7 temperature grade (0-85°C).
