EP1S20F672C7 - Stratix FPGA 18,460 LEs 672-BGA | Intel
MPN: EP1S20F672C7 β Last Time Buy| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $285 | $285.00 |
| 10 | $265 | $2,650.00 |
| 100 | $240 | $24,000.00 |
| 500 | $215 | $107,500.00 |
| 1,000 | $195 | $195,000.00 |
Drop-in alternatives for EP1S20F672C7 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EP1S20F672C7N
β Drop-Inβ In Stock
$109.2 / Unit
View Datasheet βEP1S20F672C6
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$470 / Unit
View Datasheet βEP1S20F672C6N
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$68.9 / Unit
View Datasheet βEP1S20F484C7
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$195 / Unit
View Datasheet βEP1S20B672C7N
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$320 / Unit
View Datasheet βEP1S20B672C6N
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$425 / Unit
View Datasheet βEP1S20F672C7 Maximum Ratings & Electrical Characteristics
| Series | Stratix |
| Family | Altera Stratix FPGA |
| Logic Elements (LEs) | 18,460 |
| Embedded Memory Bits | 1,669,248 |
| User I/O Pins | 426 |
| Package | 672-ball FineLine BGA (35 x 35 mm, 1.27 mm pitch) |
| Logic Family | CMOS, SRAM-based |
| Core Supply Voltage | 1.5 V |
| Operating Temperature | 0C to 85C (commercial) |
| Speed Grade | C7 |
| Configuration Modes | JTAG, Passive Serial, Fast Passive Parallel, Active Serial |
| Mounting Type | Surface Mount |
| RoHS Status | unknown |
| Clock PLLs | Up to 10 |
EP1S20F672C7 Pin Configuration
| Pin A1 | I/O β User I/O bank 1 |
| Pin A2 | I/O β User I/O bank 1 |
| Pin A3 | VCCINT β Core supply 1.5 V |
| Pin A4 | GND β Ground |
| Pin B1 | I/O β User I/O bank 1 |
| Pin B2 | I/O β User I/O bank 1 |
| Pin B3 | I/O β User I/O bank 1 |
| Pin B4 | VCCIO1 β I/O bank 1 reference voltage |
| Pin C1 | I/O β User I/O bank 1 |
| Pin C2 | I/O β User I/O bank 1 |
| Pin C3 | TCK β JTAG test clock |
| Pin C4 | TMS β JTAG test mode select |
| Pin D1 | I/O β User I/O bank 1 |
| Pin D2 | TDI β JTAG test data in |
| Pin D3 | TDO β JTAG test data out |
| Pin D4 | TRST β JTAG test reset (active low) |
| Pin E1 | I/O β User I/O bank 1 |
| Pin E2 | I/O β User I/O bank 1 |
| Pin E3 | MSEL0 β Configuration mode select bit 0 |
| Pin E4 | MSEL1 β Configuration mode select bit 1 |
| Pin F1 | nCE β Chip enable (active low) |
| Pin F2 | nCONFIG β Configuration control (active low) |
| Pin F3 | nSTATUS β Configuration status (active low) |
| Pin F4 | CONF_DONE β Configuration done indicator |
| Pin G1 | DCLK β Configuration clock |
| Pin G2 | DATA0 β Configuration data bit 0 |
| Pin G3 | PLL1_CLKp β PLL1 clock input positive |
| Pin G4 | PLL1_CLKn β PLL1 clock input negative |
| Pin H1 | VCCPD β Pre-driver supply 3.3 V |
| Pin H2 | GND β Ground |
| Pin H3 | I/O β User I/O bank 8 |
| Pin H4 | I/O β User I/O bank 8 |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EP1S20F672C7 is suitable for 6 applications: Telecommunication Line-Card Processing, DSP Co-Processing for Radar and Signal Intelligence, Test and Measurement Instrumentation, Medical Imaging Pipeline Acceleration, Industrial Motion-Control and Machine Vision, Aerospace and Defense Secure Communications.
Telecommunication Line-Card Processing
The EP1S20F672C7 fits telecommunication line-card processing because its 18,460 LEs plus 14+ dedicated DSP blocks deliver the parallel multiply-accumulate throughput required for SDH/SONET framers, multi-gigabit Ethernet bridges, and ATM/PoS switches. The 426 user I/Os accommodate backplane SERDES interfaces (LVDS/LVPECL), while 1,669,248 bits of TriMatrix memory buffer packet headers and routing tables without off-chip SRAM latency. The -C7 speed grade sustains above 200 MHz internal Fmax, sufficient for OC-48/STM-16 line rates. Unlike ASIC alternatives, the Stratix FPGA allows post-deployment protocol updates for evolving standards such as MPLS-TP and OIF-compliant OTN mappings.
Recommended
DSP Co-Processing for Radar and Signal Intelligence
The EP1S20F672C7 suits DSP co-processing for radar, sonar, and signal-intelligence systems because its dedicated hardware multipliers execute FFT, FIR, and correlation kernels at sample rates exceeding 200 MHz. The TriMatrix memory hierarchy (M512, M4K, M-RAM blocks) feeds these multipliers without contention, sustaining real-time beam-forming across hundreds of channels. The 426 I/O balls accept LVDS ADC data streams at hundreds of megahertz, while the 1.5 V core and 0.18 micrometer CMOS process deliver predictable power dissipation under sustained load. The Quartus DSP Builder toolchain accelerates MATLAB-to-FPGA datapath translation, shrinking development cycles for evolving threat libraries.
Recommended
Test and Measurement Instrumentation
The EP1S20F672C7 fits test-and-measurement instrumentation such as protocol analyzers, logic analyzers, and arbitrary waveform generators because its 426 user I/Os and reconfigurable I/O standards (LVDS, HSTL, SSTL) drive or sample wide parallel buses in real time. 1,669,248 bits of embedded memory store deep acquisition buffers, allowing multi-million-sample captures without external SRAM. The JTAG and Active Serial configuration paths enable field firmware updates over USB or Ethernet without removing the instrument from service. Compared to fixed-function ASIC instruments, the Stratix FPGA lets vendors add new protocol decoders via firmware release rather than hardware revision.
Recommended
Medical Imaging Pipeline Acceleration
The EP1S20F672C7 accelerates medical imaging pipelines (CT reconstruction, MRI back-projection, ultrasound beamforming) because its 14+ DSP blocks execute parallel MAC operations at over 200 MHz, compressing reconstruction latency from seconds to milliseconds. The 1,669,248-bit TriMatrix memory holds intermediate projection data on-chip, avoiding external DDR access stalls. 426 user I/Os accept high-speed LVDS data from detector arrays and drive DVI/HDMI preview outputs. The 1.5 V core supply simplifies power-tree design in IEC 60601-1 compliant medical equipment, while commercial 0-85C operation matches the thermal envelope of ventilated imaging carts.
Recommended
Industrial Motion-Control and Machine Vision
The EP1S20F672C7 fits industrial motion-control and machine-vision systems because its 426 user I/Os directly interface to multi-axis encoder inputs (RS-422, LVDS), PWM motor drives, and Camera Link vision sensors without bridge ASICs. The 18,460 LEs implement real-time PID loops, S-curve trajectory generators, and image-processing kernels (Sobel, threshold, connected-component labeling) at deterministic latency. TriMatrix memory buffers line-scan images at full Camera Link 80 MHz pixel rate. The 0-85C commercial temperature range suits factory-floor enclosures; engineers needing -40-100C operation specify the EP1S20F672I7 instead, sharing the same F672 footprint.
Recommended
Aerospace and Defense Secure Communications
The EP1S20F672C7 supports aerospace and defense secure communications because its SRAM-based configuration allows crypto-key reprogramming per mission while 426 user I/Os drive MIL-STD-1553, ARINC 429, and high-speed LVDS datalinks simultaneously. Dedicated hardware multipliers accelerate AES, SNOW 3G, and proprietary cipher algorithms at multi-gigabit rates. 1,669,248 bits of embedded memory hold session keys and waveform tables without external bus exposure. The commercial -C7 speed grade is acceptable for ground-station and naval applications; flight-grade deployments specify the -I7 industrial temperature variant with the same F672 BGA footprint.
Recommended
Recommended Products Summary
Engineering reference data for EP1S20F672C7 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP1S20F672C7N | EP1S20F672C6 | EP1S20F672C6N | EP1S20F484C7 | EP1S20B672C7N |
|---|---|---|---|---|---|---|
| Package | 672-ball FineLine BGA (35x35 mm) | 672-ball FineLine BGA - same | 672-ball FineLine BGA - same | 672-ball FineLine BGA - same | 484-ball FineLine BGA - smaller footprint | 672-ball FineLine BGA - same |
| Brand | Intel (formerly Altera) | Intel | Intel | Intel | Intel | Intel |
| Logic Elements | 18,460 | 18,460 | 18,460 | 18,460 | 18,460 | 18,460 |
| Embedded Memory Bits | 1,669,248 | 1,669,248 | 1,669,248 | 1,669,248 | 1,669,248 | 1,669,248 |
| User I/O Count | 426 | 426 | 426 | 426 | ~238 (-188 I/Os due to smaller package) | 426 |
| Speed Grade | C7 | C7 | C6 (faster) | C6 (faster) | C7 | C7 |
| Operating Temperature | 0C to 85C (commercial) | 0C to 85C (commercial) | 0C to 85C (commercial) | 0C to 85C (commercial) | 0C to 85C (commercial) | 0C to 85C (commercial) |
| Silicon Revision | C-step | C-step | C-step | C-step | C-step | B-step (older revision) |
| Lifecycle Status | Last Time Buy | Last Time Buy | Last Time Buy | Last Time Buy | Last Time Buy | Last Time Buy |
Key Differentiators
- Pb-free reflow compatibility with identical timing closure (vs EP1S20F672C6N)
- Maximum user I/O count in the Stratix F672 family (vs EP1S20F484C7)
- C-step silicon revision for latest errata coverage (vs EP1S20B672C7N)
Design Notes
The EP1S20F672C7 requires a regulated 1.5 V VCCINT rail with a minimum 30 A peak current capability for configuration transients, plus four independent VCCIO bank supplies (1.5 V/1.8 V/2.5 V/3.3 V) selectable per bank. Use the Quartus PowerPlay early power estimator before layout to dimension bulk decoupling. Estimated: at 50% toggle rate and 25C ambient, core current draw approaches 8-12 A; designers should provision 20 A headroom on the 1.5 V regulator to absorb in-rush during configuration. Place 470 microfarad bulk polymer and 220 microfarad ceramic decoupling within 25 mm of the BGA vias.
The F672 BGA has a junction-to-ambient thermal resistance (theta_JA) of approximately 12-15 C/W with a 1 square inch top-side heatsink. Estimated: at 6 W total power dissipation, junction temperature rises 72-90 C above ambient - within commercial limit but with no margin for confined enclosures. For industrial (-40C to 100C) operation, attach a 30 mm x 30 mm copper pad array on top of the BGA, or use a push-on pin-fin heatsink with thermal interface material. Insufficient thermal design is the primary root cause of field failures in Stratix I designs.
The 672-ball FineLine BGA with 1.27 mm pitch requires a 6-layer PCB minimum: signal-GND-signal-power-signal-GND stack-up with microvia-in-pad or staggered microvia construction for breakout. Each user I/O ball needs at least one via-in-pad for escape routing; use 0.4 mm laser-drilled microvias with 1 oz copper fill. Differential pairs (LVDS/LVPECL) must match lengths within 0.13 mm (5 mil) to preserve skew margin. Reference the Stratix Handbook Section III pin connection guidelines for unused-pin tie-off recommendations - floating configuration pins cause JTAG chain instability.
Do not leave MSEL0/MSEL1 floating - tie through 10 kilohm pull-up or pull-down resistors to select Active Serial (AS), Passive Serial (PS), or Fast Passive Parallel (FPP) configuration mode. Common errors: connecting nCONFIG to ground (latchup), failing to release OE of the configuration EPC device during power-up, and routing TCK without a 25 ohm series damping resistor. The CONF_DONE and nSTATUS open-drain outputs require external 10 kilohm pull-ups to VCCPD (3.3 V).
LVDS I/O standards on the EP1S20F672C7 require 100 ohm differential termination across the receiver pair at the far end of the transmission line. Series-termination is not recommended for Stratix LVDS because the on-chip driver already matches 100 ohm differential. Source-synchronous interfaces (DDR2, QDRII, RLDRAM) must use Stratix dedicated DQS/DQSn pins and the Quartus Pin Planner to assign the matching read-deskew logic. Failure to use dedicated DQS pins forces manual delay-line calibration and typically fails timing closure above 200 MHz.
Compliance Information
Stratix I family manufactured 2002-2007. EP1S20F672C7 is tin-lead (SnPb) ball finish; Pb-free variants (suffix N) available as EP1S20F672C7N, C6N. RoHS/REACH compliance not explicitly stated in retrieved web data - verify with Intel/Authorized distributor documentation. Not AEC-Q100 qualified (industrial, automotive users must qualify separately).
