EP1S20F672C7N - Stratix 18460-Cell FPGA, 672-FBGA | Intel | Embedded
MPN: EP1S20F672C7N ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $185 | $185.00 |
| 10 | $162.5 | $1,625.00 |
| 100 | $138.75 | $13,875.00 |
| 500 | $121.4 | $60,700.00 |
| 1,000 | $109.2 | $109,200.00 |
Drop-in alternatives for EP1S20F672C7N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP1S20F672C7
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View Datasheet →EP1S20F672C6N
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View Datasheet →EP1S20F672C6
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View Datasheet →EP1S20F672C7N Maximum Ratings & Electrical Characteristics
| Series | Stratix (first generation) |
| Family | Stratix |
| Logic Elements (LEs) | 18,460 |
| Logic Cells | 18,460 |
| Configurable Logic Blocks (CLBs) | 2,132 |
| Embedded Memory (TriMatrix) | 1,669,248 bits (426 Kbit total) |
| DSP Blocks | 56 (dedicated 18x18 multipliers) |
| Maximum User I/O | 586 |
| PLLs | Up to 12 |
| Maximum Operating Frequency | 420.17 MHz |
| Core Voltage | 1.5 V |
| Process Technology | 130 nm CMOS |
| Package | 672-FBGA (FineLine BGA) |
| Package Body Size | 35 mm x 35 mm |
| Ball Pitch | 1.27 mm |
| Operating Temperature | 0°C to +85°C (commercial) |
| Speed Grade | C7 (-7) |
| Mounting Type | Surface Mount |
| Lead-Free / RoHS | Yes (lead-free finish, RoHS compliant) |
| Configuration Modes | PS, PPS, FPP, JTAG |
EP1S20F672C7N 35 mm x 35 mm Pin Configuration Guide
Complete pinout information for EP1S20F672C7N (35 mm x 35 mm package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP1S20F672C7N.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EP1S20F672C7N is suitable for 6 applications: Telecommunications Line Card Glue Logic, Industrial Motor Control and Drive, Legacy Software-Defined Radio Front-End Buffer, Military/Aerospace Signal Processing, Embedded DSP Pre-Processing, Custom PCI / Bus Bridge Logic.
Telecommunications Line Card Glue Logic
The EP1S20F672C7N's 18,460 logic elements, 586 user I/Os, and 56 dedicated 18x18 multipliers suit it for telecom line-card glue logic that bridges network processors, SERDES, and backplane PHYs. The 1.5V core with multi-voltage I/O banks (3.3V/2.5V/1.8V/1.5V via VCCIO) allows direct connection to LVTTL, LVCMOS, SSTL, and HSTL interfaces common in telecom backplanes. With 420 MHz internal performance and up to 12 PLLs, the device can implement rate-matching FIFOs, UTOPIA/SerDes adapters, and custom packet-classification engines. The 1,669,248-bit TriMatrix memory (426 Kbit total) is sufficient for typical 4-8 KB packet buffers per port.
Recommended
Industrial Motor Control and Drive
The EP1S20F672C7N's 56 dedicated 18x18 hardware multipliers combined with 18,460 logic elements make it well suited for FOC (field-oriented control), space-vector PWM, and encoder-feedback processing in industrial drives up to ~50 kW. The device's 1.27mm-pitch 672-FBGA package is rated for industrial operating temperatures when paired with proper thermal management. The 426 Kbit TriMatrix memory holds Q-axis/d-axis reference frames and pre-computed sine/cosine LUTs without external SRAM. The 12 PLLs allow multiple PWM-aligned clock domains for inverter, ADC, and resolver interfaces. Designers typically pair the FPGA with external 16-bit ADCs and gate drivers, using the 586 I/Os to fan out signals.
Recommended
Legacy Software-Defined Radio Front-End Buffer
The EP1S20F672C7N's combination of 18,460 LEs, 56 18x18 multipliers, and 1,669,248 bits of memory targets legacy SDR front-end DSP stages such as digital down-conversion (DDC), FIR filtering, and resampling. At 420 MHz, each 18x18 multiplier supports FIR tap rates up to ~420 MSPS, and 56 multipliers allow 8-tap FIR at 56/8 = 7 channels simultaneously, or a single 56-tap channel. The TriMatrix memory (M512/M4K/MRAM blocks) supports sample buffers and NCO phase accumulators. Multi-bank I/O lets the device accept LVDS data from a wideband ADC while outputting LVTTL/LVCMOS to a downstream DSP processor.
Recommended
Military/Aerospace Signal Processing
The EP1S20F672C7N's lead-free 672-FBGA package, 130nm CMOS architecture, and 18,460 logic elements are deployed in legacy military and aerospace signal-processing subsystems where bitstream maturity and -7 speed grade are validated for the program. The device's 56 hardware multipliers support FFT/iFFT and channelization operations common in EW (electronic warfare) and SIGINT payloads. Memory-rich TriMatrix architecture simplifies sample-rate conversion, while 586 I/Os accommodate parallel ADC and DAC interfaces typical of MIL-STD-1553 and custom sensor fabrics. Designers must verify long-term supply through franchised distributors and program life-of-buy arrangements.
Recommended
Embedded DSP Pre-Processing
The EP1S20F672C7N serves as a pre-processor in imaging, video, and medical imaging pipelines where 56 dedicated 18x18 multipliers and 1,669,248 bits of embedded memory accelerate FIR filters, motion estimation, and color-space conversion before handing data to a host CPU. The -7 speed grade sustains 420 MHz fabric performance, allowing real-time processing of standard-definition video at 60 Hz. Multi-bank I/O supports concurrent connection to image sensors (LVDS) and DDR memory controllers (SSTL). Pin-compatible lower-cost variants such as the EP1S20F672C6N allow program-cost optimization once design timing is closed at -6 grade.
Recommended
Custom PCI / Bus Bridge Logic
The EP1S20F672C7N's 586 user I/Os and 12 PLLs make it well suited for custom PCI, PCI-X, and proprietary parallel-bus bridges that require multiple clock domains and protocol adaptation. The device can implement bus arbitration, scatter-gather DMA controllers, and protocol-translation state machines. The 426 Kbit TriMatrix memory supports descriptor rings and small FIFOs for short-packet workloads. Lead-free 672-FBGA packaging and 0-85°C commercial temperature rating suit industrial embedded SBC (single-board computer) designs where the FPGA handles interface translation between a host processor and legacy I/O.
Recommended
Recommended Products Summary
Engineering reference data for EP1S20F672C7N — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP1S20F672C7 | EP1S20F672C6N | EP1S20F672C6 |
|---|---|---|---|---|
| Package | 672-FBGA (35x35mm, 1.27mm pitch) | 672-FBGA (35x35mm, 1.27mm pitch) - same | 672-FBGA (35x35mm, 1.27mm pitch) - same | 672-FBGA (35x35mm, 1.27mm pitch) - same |
| Brand | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) |
| Speed Grade | C7 (-7) | C7 (-7) | C6 (-6, ~15% slower) | C6 (-6, ~15% slower) |
| Lead-Free Finish | Yes (RoHS, 'N' suffix) | No (SnPb) | Yes (RoHS) | No (SnPb) |
| Logic Elements | 18,460 | 18,460 | 18,460 | 18,460 |
| Embedded Memory | 1,669,248 bits (426 Kbit) | 1,669,248 bits (426 Kbit) | 1,669,248 bits (426 Kbit) | 1,669,248 bits (426 Kbit) |
| DSP / 18x18 Multipliers | 56 | 56 | 56 | 56 |
| Maximum User I/O | 586 | 586 | 586 | 586 |
| Core Voltage | 1.5 V | 1.5 V | 1.5 V | 1.5 V |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Lead-free RoHS-compliant finish with original -7 speed grade (vs EP1S20F672C7)
- Faster speed grade than -6 alternatives (vs EP1S20F672C6N)
- Smaller and lower-pin-count than 780-FBGA siblings (vs EP1S20F780C7N)
Design Notes
The 672-FBGA package's thermal performance is dominated by PCB copper area and thermal via count under the die. Estimated: with 1oz copper on a 4-layer JEDEC JESD51 board and a typical 5x5 thermal via array under the package, theta-JA is approximately 11-13 C/W. At 2W dissipation this yields a 22-26°C junction temperature rise above ambient; at 5W, 55-65°C. Active cooling is recommended for sustained >3W operation. Boundary-scan and JTAG-only designs with low toggle rates typically run <1W.
Place 1.5V VCCINT decoupling capacitors (0.1µF X7R) within 50 mils of every dedicated VCCINT ball, with bulk 10µF X5R capacitors distributed across the FPGA footprint. VCCIO banks each require their own decoupling network sized for the I/O toggle rate - LVDS banks need a ferrite bead plus 0.1µF + 10µF, while LVTTL banks typically need only 0.1µF + 4.7µF. VCCA_PLL pins must connect to a quiet 1.5V rail through a ferrite bead per the Stratix Handbook recommendation.
Do not attempt to synthesize a new design for this part in Quartus Prime - first-generation Stratix is supported only by Quartus II 13.0sp1 and earlier. Configuration bitstreams are incompatible with Quartus Prime. When designing for lead-free reflow, ensure the PCB profile follows JEDEC J-STD-020 with a peak body temperature of 245°C for the SnAgCu ball finish. Do not mix EP1S20F672C7 (SnPb) and EP1S20F672C7N (lead-free) on the same board, as bi-metallic solder joints are unreliable.
Compliance Information
RoHS compliance inferred from the 'N' suffix in the MPN (Altera/Intel convention for lead-free finish). REACH, halogen-free, and conflict-minerals status were not present in the verified web data and are marked 'unknown'. AEC-Q100 is not applicable because this is a commercial-grade FPGA in the C7 temperature grade (0-85°C).
