EPM7160ELC84-12 - MAX 7000 CPLD, 160 Macrocells, 12ns | Altera
부품 번호: EPM7160ELC84-12 ⚠ 최종 구매| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.95 | $1,395.00 |
| 250 | $12.4 | $3,100.00 |
| 500 | $11.1 | $5,550.00 |
EPM7160ELC84-12 개요
A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL-like macrocell arrays on a single chip. CPLDs sit between simple SPLDs (PALs/GALs) and larger FPGAs in the programmable logic hierarchy: SPLD -> CPLD -> FPGA. They offer deterministic, near-zero standby power, instant-on configuration from on-chip EEPROM, and predictable timing that is well suited to glue logic, bus decoding, and state-machine control. The MAX 7000 family uses Altera's second-generation MAX architecture fabricated in CMOS, and supports 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 JTAG interface.
Key features include 3,200 usable gates, four logic array blocks (LABs), 68 maximum user I/Os, a 12 ns pin-to-pin propagation delay with counter speeds up to 90.9 MHz, and a single 5.0 V supply (4.75 V to 5.25 V). The 'E' suffix designates the enhanced MAX 7000E variant with additional global clocks, additional output enable controls, enhanced interconnect resources, and fast input registers. In-system programmability via JTAG eliminates the need for a dedicated programmer and enables field upgrades.
Typical applications include bus decoding and address mapping in 5V microprocessor systems, glue logic between microcontrollers and peripherals, state-machine and sequencer designs, and replacement of discrete TTL/CMOS logic gates. The wide I/O count also makes it attractive for industrial control and telecommunication line-card glue functions.
When designing with the EPM7160ELC84-12, remember that the 84-pin PLCC footprint requires a through-hole or socketed footprint with J-leads, not a standard surface-mount land pattern. Plan for JTAG chain access in PCB layout to enable ISP. Total power dissipation scales with the number of toggling outputs and the toggle frequency; use Altera's Quartus II MAX+PLUS II power estimator for accurate budgeting.
This page synthesizes distributor pricing, same-family drop-in alternatives with different speed grades and temperature ratings, and practical design notes not consolidated in any single manufacturer datasheet.
드롭인 대체품: EPM7160ELC84-12 — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: EPM7160ELC84-12 (동일 폼 팩터 및 풋프린트) — 차이점: Operating Temperature, Mounting Type, Usable Gates, Package, RoHS Status.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
EPM7160ELC84-15
✅ 드롭인✓ 재고 있음
$5.95 / 개
데이터시트 보기 →EPM7160ELC84-20
✅ 드롭인✓ 재고 있음
$16.95 / 개
데이터시트 보기 →EPM7160ELC84-25
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
EPM7160ELI84-15
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
EPM7160ELI84-20
✅ 드롭인✓ 재고 있음
$11.1 / 개
데이터시트 보기 →EPM7160ELC84-12 최대 정격 & 전기적 특성
| Manufacturer | Altera (Intel PSG) |
| Series | MAX 7000 (MAX 7000E) |
| Programmable Type | EE PLD (EEPROM) |
| Number of Macrocells | 160 |
| Number of Logic Array Blocks (LABs) | 4 |
| Number of Usable Gates | 3,200 |
| Number of I/O (max) | 68 |
| Number of I/O (per package) | 64 |
| Propagation Delay tpd(1) max | 12 ns |
| Counter Frequency (max) | 90.9 MHz |
| Voltage Supply - Internal | 4.75 V to 5.25 V (5 V nominal) |
| 동작 온도 | 0C to +70C (commercial) |
| 패키지 / 케이스 | 84-LCC (J-Lead) |
| Supplier Device Package | 84-PLCC (29.31 x 29.31 mm) |
| 실장 유형 | Surface Mount |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) |
EPM7160ELC84-12 핀 구성
| 핀 1 | I/O — User I/O (function defined by design) |
| 핀 2 | I/O — User I/O (function defined by design) |
| 핀 3 | I/O — User I/O (function defined by design) |
| 핀 4 | I/O — User I/O (function defined by design) |
| 핀 5 | I/O — User I/O (function defined by design) |
| 핀 6 | I/O — User I/O (function defined by design) |
| 핀 7 | I/O — User I/O (function defined by design) |
| 핀 8 | I/O — User I/O (function defined by design) |
| 핀 9 | I/O — User I/O (function defined by design) |
| 핀 10 | I/O — User I/O (function defined by design) |
| 핀 11 | VCC — 5 V supply |
| 핀 12 | I/O — User I/O (function defined by design) |
| 핀 13 | I/O — User I/O (function defined by design) |
| 핀 14 | I/O — User I/O (function defined by design) |
| 핀 15 | I/O — User I/O (function defined by design) |
| 핀 16 | I/O — User I/O (function defined by design) |
| 핀 17 | I/O — User I/O (function defined by design) |
| 핀 18 | I/O — User I/O (function defined by design) |
| 핀 19 | I/O — User I/O (function defined by design) |
| 핀 20 | I/O — User I/O (function defined by design) |
| 핀 21 | GND — Ground |
| 핀 22 | I/O — User I/O (function defined by design) |
| 핀 23 | I/O — User I/O (function defined by design) |
| 핀 24 | I/O — User I/O (function defined by design) |
| 핀 25 | I/O — User I/O (function defined by design) |
| 핀 26 | I/O — User I/O (function defined by design) |
| 핀 27 | I/O — User I/O (function defined by design) |
| 핀 28 | I/O — User I/O (function defined by design) |
| 핀 29 | I/O — User I/O (function defined by design) |
| 핀 30 | I/O — User I/O (function defined by design) |
| 핀 31 | I/O — User I/O (function defined by design) |
| 핀 32 | I/O — User I/O (function defined by design) |
| 핀 33 | VCC — 5 V supply |
| 핀 34 | I/O — User I/O (function defined by design) |
| 핀 35 | I/O — User I/O (function defined by design) |
| 핀 36 | I/O — User I/O (function defined by design) |
| 핀 37 | I/O — User I/O (function defined by design) |
| 핀 38 | I/O — User I/O (function defined by design) |
| 핀 39 | I/O — User I/O (function defined by design) |
| 핀 40 | I/O — User I/O (function defined by design) |
| 핀 41 | I/O — User I/O (function defined by design) |
| 핀 42 | GND — Ground |
| 핀 43 | GCLK1 — Global clock input 1 (dedicated) |
| 핀 44 | OE1 — Global output enable 1 (dedicated) |
| 핀 45 | TDI — JTAG test data input |
| 핀 46 | TMS — JTAG test mode select |
| 핀 47 | TCK — JTAG test clock |
| 핀 48 | I/O — User I/O (function defined by design) |
| 핀 49 | I/O — User I/O (function defined by design) |
| 핀 50 | I/O — User I/O (function defined by design) |
| 핀 51 | I/O — User I/O (function defined by design) |
| 핀 52 | I/O — User I/O (function defined by design) |
| 핀 53 | I/O — User I/O (function defined by design) |
| 핀 54 | I/O — User I/O (function defined by design) |
| 핀 55 | I/O — User I/O (function defined by design) |
| 핀 56 | I/O — User I/O (function defined by design) |
| 핀 57 | I/O — User I/O (function defined by design) |
| 핀 58 | I/O — User I/O (function defined by design) |
| 핀 59 | I/O — User I/O (function defined by design) |
| 핀 60 | VCC — 5 V supply |
| 핀 61 | I/O — User I/O (function defined by design) |
| 핀 62 | I/O — User I/O (function defined by design) |
| 핀 63 | I/O — User I/O (function defined by design) |
| 핀 64 | I/O — User I/O (function defined by design) |
| 핀 65 | I/O — User I/O (function defined by design) |
| 핀 66 | I/O — User I/O (function defined by design) |
| 핀 67 | I/O — User I/O (function defined by design) |
| 핀 68 | I/O — User I/O (function defined by design) |
| 핀 69 | GCLK2 — Global clock input 2 (dedicated) |
| 핀 70 | OE2 — Global output enable 2 (dedicated) |
| 핀 71 | TDO — JTAG test data output |
| 핀 72 | I/O — User I/O (function defined by design) |
| 핀 73 | I/O — User I/O (function defined by design) |
| 핀 74 | I/O — User I/O (function defined by design) |
| 핀 75 | I/O — User I/O (function defined by design) |
| 핀 76 | I/O — User I/O (function defined by design) |
| 핀 77 | I/O — User I/O (function defined by design) |
| 핀 78 | I/O — User I/O (function defined by design) |
| 핀 79 | I/O — User I/O (function defined by design) |
| 핀 80 | I/O — User I/O (function defined by design) |
| 핀 81 | I/O — User I/O (function defined by design) |
| 핀 82 | I/O — User I/O (function defined by design) |
| 핀 83 | I/O — User I/O (function defined by design) |
| 핀 84 | GND — Ground |
일반적인 애플리케이션
EPM7160ELC84-12 적합 용도: 6 애플리케이션s: Microprocessor Bus Decoding and Address Mapping, Industrial Control and Factory Automation Glue Logic, Legacy Replacement of Discrete 74-Series TTL/CMOS Gates, Telecommunication Line-Card Control Logic, State-Machine and Sequencer Designs, LED Display and Sign Multiplexing.
Microprocessor Bus Decoding and Address Mapping
The EPM7160ELC84-12 is well suited to microprocessor bus decoding because its 160 macrocells and 64 user I/Os can absorb an entire 8/16/32-bit address decode tree plus chip-select glue, replacing dozens of 74-series TTL gates on a single 5 V device. Its 12 ns pin-to-pin delay keeps the decoded chip-select ahead of typical 80C186/68k/8086 access times (typically 30-60 ns), and its deterministic, instant-on EEPROM-based configuration means there is no firmware boot delay on power-up. Designers typically instantiate one LAB per major decode region (e.g. boot ROM, SRAM, peripheral block) and use the global clock pins for synchronous qualifier logic. Because the device runs from a single 5 V rail with no separate core voltage, it is a drop-in upgrade from legacy bipolar or CMOS PLDs without disturbing the existing power tree.
추천
Industrial Control and Factory Automation Glue Logic
In industrial 24V/5V control systems, the EPM7160ELC84-12 serves as the central glue-logic device that interfaces sensor inputs, opto-isolated control lines, and 5 V peripheral ICs with the host microcontroller. Its 64 user I/Os handle multiple input debouncing, latching, and output muxing channels in parallel, while its 12 ns tpd and 90.9 MHz counter rate support encoder quadrature decoding or PWM-timing peripherals on-chip. Commercial temperature (0C to +70C) is acceptable for cabinet-mounted equipment; the EPM7160ELI84-20 industrial variant is recommended when the device sits outside the enclosure. The 84-pin PLCC package is robust to vibration when socketed, and JTAG ISP allows field firmware updates for I/O protocol changes. Designers should budget I/O count carefully because MAX 7000 I/Os are 5 V TTL only - level shifting is required for 3.3 V peripherals.
추천
Legacy Replacement of Discrete 74-Series TTL/CMOS Gates
The EPM7160ELC84-12 is frequently used as a board-level consolidation replacement for clusters of 74LS, 74HC, and 74F-series glue-logic ICs, replacing up to 40-60 small-scale packages with a single PLCC-84 CPLD. This reduces PCB area, power consumption (a single 5 V CPLD vs. dozens of separate ICs each with their own quiescent draw), and BOM cost on legacy designs being refreshed. Designers port the schematic one-for-one into Altera MAX+PLUS II HDL (AHDL) or VHDL, run a quick fit, and verify timing with the simulator - the deterministic MAX 7000E timing model makes this fast and predictable. The 12 ns grade is recommended for designs that originally used 74F or 74AS logic; designs originally on 74LS or 74HC have generous timing margin and can use the cheaper -15 or -20 grade. JTAG ISP lets the board be reworked without desoldering.
추천
Telecommunication Line-Card Control Logic
In T1/E1, ISDN, and legacy PSTN line-card designs, the EPM7160ELC84-12 provides deterministic, near-zero standby power for supervisory control logic such as relay drivers, line-feed control, ring-trip detection, and codec interface glue. The single 5 V supply, 64 I/Os, and JTAG ISP are well matched to the 5 V backplane power rails typical in telecom hardware. Its 12 ns tpd supports HDLC or voice-band framing functions at standard 1.544/2.048 MHz rates with margin to spare. The MAX 7000 family was a long-standing choice in this segment because of its 5 V tolerance, in-system reprogrammability for protocol upgrades, and wide operating-temperature grade (industrial variant for outdoor cabinets). Engineers should verify the 5 V I/O tolerance against newer 3.3 V codec devices and add bus switches or level shifters if mixing voltage domains.
추천
State-Machine and Sequencer Designs
For power-supply sequencing, motor-control state machines, and test-instrument sequencers, the EPM7160ELC84-12 delivers predictable, deterministic timing that fits the problem perfectly. The 160 macrocells can encode a 16-state FSM with output-decoded actions plus parallel register banks for status flags, and the four dedicated global clocks drive state-machine clocks, capture clocks, and PWM carriers independently. Because the device is EEPROM-based, the state-machine design powers up already configured - critical for safety logic where the supervisor must come out of reset in a known state, not waiting for SRAM-based configuration. The 12 ns pin-to-pin delay lets the CPLD resolve state-machine outputs within one fast-clock period, supporting sequencers with up to 90 MHz internal state-update rates. Designers should document state encodings and unused-pin states explicitly because unused macrocells still consume a small standby current.
추천
LED Display and Sign Multiplexing
Large LED matrix signs and 7-segment display panels often use a CPLD such as the EPM7160ELC84-12 to drive row/column multiplexers, generate blanking intervals, and handle brightness modulation. Its 64 user I/Os can directly drive a 16x32 single-color matrix or a 7-segment display cluster, and the 90.9 MHz counter rate supports high-refresh-rate PWM dimming without flicker. The 5 V TTL outputs match the drive requirement of most LED driver ICs, eliminating external buffers. Because each design is unique, designers use MAX+PLUS II to specify pin assignments manually, keeping high-frequency switching outputs away from sensitive analog lines on the board. For RGB panels, the 64-I/O budget is often tight - consider migrating to a larger MAX 7000 device (EPM7256S) or a small FPGA for color-depth expansion.
추천
추천 제품 요약
엔지니어링 참조 데이터: EPM7160ELC84-12 — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | EPM7160ELC84-15 | EPM7160ELC84-20 | EPM7160ELC84-25 | EPM7160ELI84-15 | EPM7160ELI84-20 |
|---|---|---|---|---|---|---|
| Brand | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) |
| Package | 84-PLCC (J-Lead) - same | 84-PLCC (J-Lead) | 84-PLCC (J-Lead) | 84-PLCC (J-Lead) | 84-PLCC (J-Lead) | 84-PLCC (J-Lead) |
| Propagation Delay tpd(1) max | 12 ns | 15 ns (+25%) | 20 ns (+67%) | 25 ns (+108%) | 15 ns (+25%) | 20 ns (+67%) |
| Macrocells | 160 | 160 | 160 | 160 | 160 | 160 |
| Logic Array Blocks | 4 | 4 | 4 | 4 | 4 | 4 |
| User I/O (this package) | 64 | 64 | 64 | 64 | 64 | 64 |
| Usable Gates | 3,200 | 3,200 | 3,200 | 3,200 | 3,200 | 3,200 |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C (commercial) | 0C to +70C (commercial) | 0C to +70C (commercial) | -40C to +85C (industrial) | -40C to +85C (industrial) |
| Supply Voltage | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V |
| In-System Programmability | Yes (JTAG IEEE 1149.1) | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) |
주요 차별점
- Highest speed grade in MAX 7000E 84-pin PLCC family (vs EPM7160ELC84-15)
- Commercial temperature grade optimized for controlled-environment deployments (vs EPM7160ELI84-20)
- 160 macrocells and 64 I/Os balance density vs cost in the MAX 7000E line (vs EPM7128ELC84-12 (128 macrocells, same PLCC-84))
설계 노트
The 84-pin PLCC package is NOT pin-compatible with any QFP/TQFP package in the same MAX 7000 family; migrating between packages requires PCB redesign. Verify that PCB layout reserves clearance for the J-lead footprint (recommended land pattern per IPC-7351 PLCC-84) and consider a PLCC-84 socket for prototype rework. JTAG pins (TDI/TDO/TMS/TCK on pins 45-47 and 71) must be brought out to a header or test pad - burying them prevents in-system programming and field firmware upgrades, which is the primary benefit of the MAX 7000 family over legacy PROMs.
The MAX 7000E ICC quiescent current is approximately 5-15 mA standby; dynamic current scales with the number of toggling outputs and the toggle frequency. Estimate: I_dynamic ~= N_outputs * C_load * VCC * f_toggle. With all 64 I/Os at 10 MHz into 50 pF loads, expect an additional ~80 mA on top of standby. Place 0.1 uF ceramic decoupling caps close to every VCC pin (4 VCC pins: 11, 33, 60 plus a fourth; cross-reference the package pinout) and a single 10 uF tantalum/ceramic bulk cap at the supply entry.
Keep JTAG chain routing short and isolated from high-frequency switching signals. The TCK pin is particularly sensitive - long traces pick up noise and cause JTAG programming failures. If the design includes other JTAG devices on the same chain (e.g. microcontrollers, FPGAs), order the chain so that the CPLD is bypass-friendly and verify the chain with Altera's JTAG chain debugger tool before depending on field upgrades. Reserve unused I/Os as outputs tied low (not inputs floating) to minimize standby current.
MAX 7000E I/O buffers are 5 V TTL-compatible with edge rates around 1-2 ns. For bus speeds above 25 MHz, add 33 ohm series-termination resistors on heavily-loaded outputs to dampen ringing. Avoid routing outputs adjacent to analog sections of the board; the CPLD is not a quiet part. For designs that mix 3.3 V peripherals, add bus switches (e.g. 74CBTLV3253) or level-shifters - the MAX 7000 outputs are not 3.3 V-tolerant on the inputs.
규정 준수 정보
RoHS/REACH/lead-free status not stated in the verified web data for the EPM7160ELC84-12. The MAX 7000 family includes both lead and lead-free variants - confirm the specific finish code with the distributor before ordering for RoHS-compliant assemblies. AEC-Q100 not applicable - this is a commercial-grade logic device, not an automotive-qualified part.
