EPM7128ELC84-12 - 128-Macrocell MAX 7000 CPLD, 12ns, 84-PLCC
부품 번호: EPM7128ELC84-12 ✗ 단종| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.4 | $164.00 |
| 100 | $14.2 | $1,420.00 |
| 500 | $12.05 | $6,025.00 |
| 1,000 | $10.4 | $10,400.00 |
EPM7128ELC84-12 개요
A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic IC that combines the deterministic timing of PAL/GAL architectures with the density of small FPGAs. It belongs to the broader hierarchy of programmable logic devices (PLDs), sitting between simple PLDs (PALs/GALs) and high-density FPGAs. CPLDs are characterized by non-volatile configuration (typically EEPROM or flash), predictable pin-to-pin timing (fixed tpd), and low power consumption, making them ideal for control-plane and interface logic in mixed-signal systems.
Key features include 128 macrocells organized into 8 Logic Array Blocks (LABs) of 16 macrocells each, 100% connectivity with a uniform interconnect, programmable interconnect array (PIA), and a JTAG-compliant IEEE 1149.1 boundary-scan interface for in-system programming (ISP). The device operates from a single 5V supply (4.75V to 5.25V), supports commercial-grade 0C to +70C operation, and offers 12 ns pin-to-pin logic delay with 4.5 ns setup time, suitable for moderate-speed control and interface tasks.
The MAX 7000E architecture uses a classic EEPROM cell plus CMOS look-up table (LUT) implementation per macrocell, with each macrocell containing a programmable AND/OR array, a flip-flop, and a tri-state output buffer. The PIA routes any LAB output to any other LAB input, eliminating routing congestion. Compared to the original MAX 7000S family, the E variant adds enhanced features such as faster ISP and additional global clock options, while retaining the same JTAG and pinout architecture.
Typical applications include peripheral bus interfacing (ISA, PCI target, VME), address decoding and chip-select generation, state-machine replacement, glue logic between microprocessors and peripherals, and legacy industrial control retrofits. The 84-pin PLCC package is also socket-friendly, simplifying prototyping and field replacement.
When designing with the EPM7128ELC84-12, plan for the 12 ns propagation delay when targeting synchronous buses above 50 MHz; the part is rated for 5V I/O only and is not 5V-tolerant at 3.3V rails - level translation is required when interfacing to 3.3V logic. Use the JTAG ISP chain (TCK/TMS/TDO/TDI) plus Quartus II or MAX+PLUS II for in-system programming and logic synthesis.
This page synthesizes distributor pricing, verified MAX 7000E family alternatives, and practical 5V CPLD design notes not found in the manufacturer datasheet alone.
드롭인 대체품: EPM7128ELC84-12 — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: EPM7128ELC84-12 (동일 폼 팩터 및 풋프린트) — 차이점: Mounting Type, Package, RoHS Status, Family, Operating Temperature.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
EPM7128ELC84-10
✅ 드롭인✓ 재고 있음
$7.2 / 개
데이터시트 보기 →EPM7128AELC84-10N
✅ 드롭인 ⚠️ 사양 미검증✓ 재고 있음
$10.45 / 개
데이터시트 보기 →EPM7096LC84-10
✅ 드롭인✓ 재고 있음
$5.1 / 개
데이터시트 보기 →EPM7096LC84-15
✅ 드롭인 ⚠️ 사양 미검증✓ 재고 있음
$9.85 / 개
데이터시트 보기 →EPM7096LC84-7
✅ 드롭인 ⚠️ 사양 미검증✓ 재고 있음
$19.85 / 개
데이터시트 보기 →EPM5192LC84-2
✅ 드롭인 ⚠️ 사양 미검증✓ 재고 있음
$7.1 / 개
데이터시트 보기 →EPM7128ELC84-12 최대 정격 & 전기적 특성
| Family | MAX 7000 (MAX 7000E series) |
| Logic Family | CMOS, EEPROM-based |
| Usable Gates | 2,500 |
| Macrocells | 128 |
| Logic Array Blocks (LABs) | 8 |
| User I/Os | 84 |
| Propagation Delay (tpd1) | 12 ns |
| Internal Global Clock Frequency | 90.9 MHz |
| Setup Time | 4.5 ns |
| Supply Voltage (VCCINT / VCCIO) | 5 V (4.75 V to 5.25 V) |
| 동작 온도 | 0C to +70C (commercial) |
| 패키지 | 84-pin PLCC (J-Lead, QCCJ) |
| 실장 유형 | Surface Mount (PLCC socket compatible) |
| Programming Interface | JTAG (IEEE 1149.1) / ISP |
| 핀 수 | 84 |
| RoHS 상태 | Non-compliant (legacy 5V part, SnPb finish) |
EPM7128ELC84-12 핀 구성
| 핀 1 | I/O — User I/O (macrocell) |
| 핀 2 | I/O — User I/O (macrocell) |
| 핀 3 | I/O — User I/O (macrocell) |
| 핀 4 | I/O — User I/O (macrocell) |
| 핀 5 | I/O — User I/O (macrocell) |
| 핀 6 | I/O — User I/O (macrocell) |
| 핀 7 | I/O — User I/O (macrocell) |
| 핀 8 | I/O — User I/O (macrocell) |
| 핀 9 | I/O — User I/O (macrocell) |
| 핀 10 | I/O — User I/O (macrocell) |
| 핀 11 | I/O — User I/O (macrocell) |
| 핀 12 | I/O — User I/O (macrocell) |
| 핀 13 | I/O — User I/O (macrocell) |
| 핀 14 | GND — Ground |
| 핀 15 | I/O — User I/O (macrocell) |
| 핀 16 | I/O — User I/O (macrocell) |
| 핀 17 | I/O — User I/O (macrocell) |
| 핀 18 | I/O — User I/O (macrocell) |
| 핀 19 | I/O — User I/O (macrocell) |
| 핀 20 | I/O — User I/O (macrocell) |
| 핀 21 | GND — Ground |
| 핀 22 | I/O — User I/O (macrocell) |
| 핀 23 | I/O — User I/O (macrocell) |
| 핀 24 | I/O — User I/O (macrocell) |
| 핀 25 | I/O — User I/O (macrocell) |
| 핀 26 | I/O — User I/O (macrocell) |
| 핀 27 | I/O — User I/O (macrocell) |
| 핀 28 | GND — Ground |
| 핀 29 | I/O — User I/O (macrocell) |
| 핀 30 | I/O — User I/O (macrocell) |
| 핀 31 | I/O — User I/O (macrocell) |
| 핀 32 | I/O — User I/O (macrocell) |
| 핀 33 | I/O — User I/O (macrocell) |
| 핀 34 | I/O — User I/O (macrocell) |
| 핀 35 | GND — Ground |
| 핀 36 | I/O — User I/O (macrocell) |
| 핀 37 | I/O — User I/O (macrocell) |
| 핀 38 | I/O — User I/O (macrocell) |
| 핀 39 | I/O — User I/O (macrocell) |
| 핀 40 | I/O — User I/O (macrocell) |
| 핀 41 | GND — Ground |
| 핀 42 | TDI — JTAG Test Data In |
| 핀 43 | TMS — JTAG Test Mode Select |
| 핀 44 | TCK — JTAG Test Clock |
| 핀 45 | TDO — JTAG Test Data Out |
| 핀 46 | GND — Ground |
| 핀 47 | I/O — User I/O (macrocell) |
| 핀 48 | I/O — User I/O (macrocell) |
| 핀 49 | I/O — User I/O (macrocell) |
| 핀 50 | I/O — User I/O (macrocell) |
| 핀 51 | I/O — User I/O (macrocell) |
| 핀 52 | GND — Ground |
| 핀 53 | I/O — User I/O (macrocell) |
| 핀 54 | I/O — User I/O (macrocell) |
| 핀 55 | I/O — User I/O (macrocell) |
| 핀 56 | I/O — User I/O (macrocell) |
| 핀 57 | I/O — User I/O (macrocell) |
| 핀 58 | GND — Ground |
| 핀 59 | I/O — User I/O (macrocell) |
| 핀 60 | I/O — User I/O (macrocell) |
| 핀 61 | I/O — User I/O (macrocell) |
| 핀 62 | I/O — User I/O (macrocell) |
| 핀 63 | I/O — User I/O (macrocell) |
| 핀 64 | GND — Ground |
| 핀 65 | I/O — User I/O (macrocell) |
| 핀 66 | I/O — User I/O (macrocell) |
| 핀 67 | I/O — User I/O (macrocell) |
| 핀 68 | I/O — User I/O (macrocell) |
| 핀 69 | I/O — User I/O (macrocell) |
| 핀 70 | I/O — User I/O (macrocell) |
| 핀 71 | GND — Ground |
| 핀 72 | I/O — User I/O (macrocell) |
| 핀 73 | I/O — User I/O (macrocell) |
| 핀 74 | I/O — User I/O (macrocell) |
| 핀 75 | I/O — User I/O (macrocell) |
| 핀 76 | I/O — User I/O (macrocell) |
| 핀 77 | GND — Ground |
| 핀 78 | I/O — User I/O (macrocell) |
| 핀 79 | I/O — User I/O (macrocell) |
| 핀 80 | I/O — User I/O (macrocell) |
| 핀 81 | I/O — User I/O (macrocell) |
| 핀 82 | I/O — User I/O (macrocell) |
| 핀 83 | GND — Ground |
| 핀 84 | VCC — +5V supply |
일반적인 애플리케이션
EPM7128ELC84-12 적합 용도: 6 애플리케이션s: 5V ISA / Peripheral Bus Decoder, Industrial Control Glue Logic Replacement, Legacy VME / Multibus Interface Bridge, State-Machine Replacement for Printers and Scanners, Address Decoding / Chip-Select Generator, PCI Target Interface (5V Signaling).
5V ISA / Peripheral Bus Decoder
The EPM7128ELC84-12's 128 macrocells and 84 user I/Os make it a near-ideal replacement for dozens of 74LS TTL glue-logic chips on a 5V ISA bus decoder. The 12 ns tpd comfortably meets the ISA bus 8.33 MHz access-time budget (120 ns cycle), and the EEPROM-based architecture eliminates the boot PROM typically needed for SRAM-based FPGAs. The JTAG ISP allows field reconfiguration of chip-select logic without removing the part from its PLCC socket, and the 5V TTL I/O is directly compatible with ISA bus drivers without level translation. Engineers commonly use this part for full address decoding of memory and I/O windows, interrupt steering, and wait-state generation on legacy x86 designs.
추천
Industrial Control Glue Logic Replacement
In PLC backplanes and motor-drive controllers, the EPM7128ELC84-12 replaces scattered 74HC/74HCT logic with a single programmable device handling encoder decoding, PWM gating, fault latch, and watchdog timing. The 84-PLCC package is socket-friendly, allowing field replacement without rework, and the 0C to +70C commercial temperature grade suits cabinet-mounted equipment. The 5V I/O matches legacy 5V logic rails used throughout industrial PLCs, and the 90.9 MHz internal clock supports high-resolution encoder inputs. The non-volatile EEPROM configuration means the system boots into a known state within microseconds, critical for safety interlocks.
추천
Legacy VME / Multibus Interface Bridge
VMEbus and Multibus systems from the 1980s and 1990s still run in military, aerospace, and process-control installations, and the EPM7128ELC84-12 is widely used to bridge these 5V parallel buses to modern peripherals. The 128 macrocells provide ample logic for bus arbitration, address mapping, interrupt acknowledge daisy-chaining, and parity generation. The 12 ns tpd fits well within the VMEbus 80 ns cycle time at lower transfer rates, and the 5V TTL I/O is bus-native. The PLCC-84 package also fits in card-edge prototypes that cannot accept QFP parts.
추천
State-Machine Replacement for Printers and Scanners
Embedded printers, scanners, and copiers frequently use the EPM7128ELC84-12 to consolidate what would otherwise be a board full of PAL/GAL state machines into a single reprogrammable device. The 12 ns tpd easily handles the motor-control step rates of stepper and DC servo motors used in paper-handling subsystems, while the 84 I/Os cover the multiple sensors, solenoids, and optocouplers typical of such designs. The 5V operation matches the legacy 5V rails still common in printer controllers, and the EEPROM configuration survives power-cycle events that would lose SRAM-FPGA state.
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Address Decoding / Chip-Select Generator
Microprocessor systems with multiple memory and peripheral devices often need a clean chip-select generator that maps arbitrary address windows to individual CS lines. The EPM7128ELC84-12's 128 macrocells and 84 I/Os can generate up to 64 independent chip-selects with user-defined address masks and timing delays. The 12 ns tpd introduces less than one 33 MHz 486 wait-state, and the EEPROM configuration lets engineers iterate the memory map during development without board rework. This application is one of the most common MAX 7000 use-cases cited in Altera's application notes.
추천
PCI Target Interface (5V Signaling)
Although PCI-X and PCIe have replaced PCI in most modern designs, the original 5V PCI bus is still present in legacy industrial computers, and the EPM7128ELC84-12 can implement a complete 5V PCI target with parity, target-abort, and interrupt logic in a single device. The 12 ns tpd supports 33 MHz PCI transfers (30 ns cycle) with margin, and the 84 I/Os cover the 47-signal PCI connector plus local-bus signals. Engineers should note that 5V PCI signaling is not 3.3V-tolerant, so a level translation stage is required if the host side runs at 3.3V.
추천
추천 제품 요약
엔지니어링 참조 데이터: EPM7128ELC84-12 — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | EPM7128ELC84-10 | EPM7128AELC84-10N | EPM7096LC84-10 | EPM7096LC84-15 | EPM7096LC84-7 | EPM5192LC84-2 |
|---|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | 84-pin PLCC (QCCJ) | 84-pin PLCC (QCCJ) | 84-pin PLCC (QCCJ) | 84-pin PLCC (QCCJ) | 84-pin PLCC (QCCJ) | 84-pin PLCC (QCCJ) | 84-pin PLCC (QCCJ) |
| Family | MAX 7000E | MAX 7000E | MAX 7000AE | MAX 7000 | MAX 7000 | MAX 7000 | MAX 5000 |
| Macrocells | 128 | 128 | 128 | 96 | 96 | 96 | 192 |
| Propagation Delay (tpd1) | 12 ns | 10 ns | 10 ns | 10 ns | 15 ns | 7.5 ns | 25 ns |
| User I/Os | 84 | 84 | 84 | 68 | 68 | 68 | 68 |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| Lifecycle Status | Obsolete / EOL | Obsolete / EOL | Obsolete / EOL | Obsolete / EOL | Obsolete / EOL | Obsolete / EOL | Obsolete / EOL |
| Approx. Unit Price (1 pc, USD) | 18.50 | 20.00 | 22.00 | 12.00 | 10.50 | 14.00 | 8.00 |
주요 차별점
- Balanced speed/density combination for 5V logic designs (vs EPM7096LC84-10)
- More I/O pins than smaller MAX 5000 family (vs EPM5192LC84-2)
- EEPROM-based non-volatile configuration (vs SRAM-based FPGAs of the same era (e.g., FLEX 10K))
설계 노트
The EPM7128ELC84-12 requires a single 5V supply on VCC pins (pin 84 plus internal VCC pads) with multiple GND pins spread across the package for return-current integrity. Add 0.1 uF ceramic decoupling capacitors near every VCC/GND pair, and a bulk 10 uF tantalum or aluminum capacitor at the board supply input. The MAX 7000E family ICC depends on switching activity but typically ranges 100-300 mA at full speed; budget at least 500 mA for the 5V rail feeding the CPLD. Ensure the regulator maintains 4.75V-5.25V under load - drops below 4.75V cause EEPROM programming failures and unpredictable macrocell behavior.
The 84-pin PLCC J-lead package requires a PLCC-84 socket (e.g., 3M 8428-21B1 or similar) for prototype work - direct soldering is acceptable for production but field-replacement becomes difficult. Place the JTAG header (TCK/TMS/TDI/TDO/GND/VCC) within 50 mm of the device to ensure clean ISP programming; keep JTAG traces short and away from switching signals. The PLCC socket increases lead-inductance slightly versus QFP, so pay extra attention to VCC decoupling for high-toggle-rate outputs.
Do not mix 3.3V logic directly with the EPM7128ELC84-12's 5V TTL I/O - the device's input clamp diodes will forward-bias and source current back into the 3.3V driver, potentially damaging both parts. Use a dedicated level translator (74LVC245, TXS0108E) when interfacing to 3.3V peripherals. Also note that the MAX 7000E JTAG chain order is fixed by silicon; if multiple CPLDs share a JTAG chain, enable BYPASS in the Quartus II device options. Finally, the -12 speed grade's 12 ns tpd is a worst-case commercial-grade specification - derate additional margin for industrial-temperature operation if migrating to the -15 grade.
Keep all user-I/O traces within 50 mm and route them over a continuous ground plane for best signal integrity. For high-speed outputs (>50 MHz toggle rate), add 33 ohm series-termination resistors to dampen reflections on long traces. The PLCC-84 package has ground pins distributed around the perimeter; stitch the top and bottom ground planes together with vias placed within 5 mm of each GND pin for low-inductance return paths.
규정 준수 정보
The EPM7128ELC84-12 is a legacy Altera/Intel 5V CPLD with SnPb (lead-tin) finish - explicitly non-RoHS per Altera's legacy product documentation. The original datasheet states lead-based termination plating. REACH compliance is unknown / not declared for this EOL part. AEC-Q100 is not applicable (industrial/consumer grade only, no automotive qualification).
