EPM7160ELI84-20 - MAX 7000 CPLD, 160 Macrocells, 5V, 84-PLCC | Intel
MPN: EPM7160ELI84-20 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $14.05 | $1,405.00 |
| 500 | $12.4 | $6,200.00 |
| 1,000 | $11.1 | $11,100.00 |
Drop-in alternatives for EPM7160ELI84-20 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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EPM7160ELC84-20
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View Datasheet βEPM7160ELI84-20 Maximum Ratings & Electrical Characteristics
| Series | MAX 7000 |
| Device Family | MAX 7000 (Complex Programmable Logic Device) |
| Number of Macrocells | 160 |
| Number of Logic Array Blocks (LABs) | 4 |
| Usable Gates | 3.2K |
| Number of User I/O Pins | 64 |
| Maximum Operating Frequency | 62.5 MHz |
| Pin-to-Pin Propagation Delay (tPD) | 20 ns (speed grade '-20') |
| Supply Voltage (VCC) | 5.0 V |
| Process Technology | CMOS, EEPROM-based configuration |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) |
| Programmable Security | Yes (security bit) |
| Package | 84-Pin PLCC (J-Lead) |
| Mounting Type | Surface Mount |
| Operating Temperature | -40C to +85C (Industrial grade 'I') |
| RoHS Status | Not Compliant (per Arrow listing) |
| Configuration Memory | Non-volatile EEPROM (instant-on) |
EPM7160ELI84-20 Pin Configuration
| Pin 1 | I/O β User I/O pin (pin function programmable) |
| Pin 2 | I/O β User I/O pin (pin function programmable) |
| Pin 3 | I/O β User I/O pin (pin function programmable) |
| Pin 4 | I/O β User I/O pin (pin function programmable) |
| Pin 5 | I/O β User I/O pin (pin function programmable) |
| Pin 6 | I/O β User I/O pin (pin function programmable) |
| Pin 7 | I/O β User I/O pin (pin function programmable) |
| Pin 8 | I/O β User I/O pin (pin function programmable) |
| Pin 9 | I/O β User I/O pin (pin function programmable) |
| Pin 10 | I/O β User I/O pin (pin function programmable) |
| Pin 11 | GND β Ground |
| Pin 12 | I/O β User I/O pin (pin function programmable) |
| Pin 13 | I/O β User I/O pin (pin function programmable) |
| Pin 14 | I/O β User I/O pin (pin function programmable) |
| Pin 15 | I/O β User I/O pin (pin function programmable) |
| Pin 16 | I/O β User I/O pin (pin function programmable) |
| Pin 17 | I/O β User I/O pin (pin function programmable) |
| Pin 18 | I/O β User I/O pin (pin function programmable) |
| Pin 19 | I/O β User I/O pin (pin function programmable) |
| Pin 20 | I/O β User I/O pin (pin function programmable) |
| Pin 21 | GND β Ground |
| Pin 22 | I/O β User I/O pin (pin function programmable) |
| Pin 23 | I/O β User I/O pin (pin function programmable) |
| Pin 24 | I/O β User I/O pin (pin function programmable) |
| Pin 25 | I/O β User I/O pin (pin function programmable) |
| Pin 26 | I/O β User I/O pin (pin function programmable) |
| Pin 27 | I/O β User I/O pin (pin function programmable) |
| Pin 28 | I/O β User I/O pin (pin function programmable) |
| Pin 29 | I/O β User I/O pin (pin function programmable) |
| Pin 30 | I/O β User I/O pin (pin function programmable) |
| Pin 31 | GND β Ground |
| Pin 32 | I/O β User I/O pin (pin function programmable) |
| Pin 33 | I/O β User I/O pin (pin function programmable) |
| Pin 34 | I/O β User I/O pin (pin function programmable) |
| Pin 35 | I/O β User I/O pin (pin function programmable) |
| Pin 36 | I/O β User I/O pin (pin function programmable) |
| Pin 37 | I/O β User I/O pin (pin function programmable) |
| Pin 38 | I/O β User I/O pin (pin function programmable) |
| Pin 39 | I/O β User I/O pin (pin function programmable) |
| Pin 40 | I/O β User I/O pin (pin function programmable) |
| Pin 41 | GND β Ground |
| Pin 42 | I/O β User I/O pin (pin function programmable) |
| Pin 43 | TDI β JTAG Test Data In (IEEE 1149.1) |
| Pin 44 | TMS β JTAG Test Mode Select (IEEE 1149.1) |
| Pin 45 | TCK β JTAG Test Clock (IEEE 1149.1) |
| Pin 46 | I/O β User I/O pin (pin function programmable) |
| Pin 47 | I/O β User I/O pin (pin function programmable) |
| Pin 48 | I/O β User I/O pin (pin function programmable) |
| Pin 49 | I/O β User I/O pin (pin function programmable) |
| Pin 50 | I/O β User I/O pin (pin function programmable) |
| Pin 51 | GND β Ground |
| Pin 52 | I/O β User I/O pin (pin function programmable) |
| Pin 53 | I/O β User I/O pin (pin function programmable) |
| Pin 54 | I/O β User I/O pin (pin function programmable) |
| Pin 55 | I/O β User I/O pin (pin function programmable) |
| Pin 56 | I/O β User I/O pin (pin function programmable) |
| Pin 57 | I/O β User I/O pin (pin function programmable) |
| Pin 58 | I/O β User I/O pin (pin function programmable) |
| Pin 59 | I/O β User I/O pin (pin function programmable) |
| Pin 60 | I/O β User I/O pin (pin function programmable) |
| Pin 61 | GND β Ground |
| Pin 62 | I/O β User I/O pin (pin function programmable) |
| Pin 63 | I/O β User I/O pin (pin function programmable) |
| Pin 64 | I/O β User I/O pin (pin function programmable) |
| Pin 65 | I/O β User I/O pin (pin function programmable) |
| Pin 66 | I/O β User I/O pin (pin function programmable) |
| Pin 67 | I/O β User I/O pin (pin function programmable) |
| Pin 68 | I/O β User I/O pin (pin function programmable) |
| Pin 69 | I/O β User I/O pin (pin function programmable) |
| Pin 70 | I/O β User I/O pin (pin function programmable) |
| Pin 71 | GND β Ground |
| Pin 72 | I/O β User I/O pin (pin function programmable) |
| Pin 73 | I/O β User I/O pin (pin function programmable) |
| Pin 74 | I/O β User I/O pin (pin function programmable) |
| Pin 75 | I/O β User I/O pin (pin function programmable) |
| Pin 76 | I/O β User I/O pin (pin function programmable) |
| Pin 77 | TDO β JTAG Test Data Out (IEEE 1149.1) |
| Pin 78 | GND β Ground |
| Pin 79 | I/O β User I/O pin (pin function programmable) |
| Pin 80 | I/O β User I/O pin (pin function programmable) |
| Pin 81 | I/O β User I/O pin (pin function programmable) |
| Pin 82 | I/O β User I/O pin (pin function programmable) |
| Pin 83 | I/O β User I/O pin (pin function programmable) |
| Pin 84 | VCC β +5.0V supply voltage |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM7160ELI84-20 is suitable for 6 applications: Industrial Control & Factory Automation, Telecommunications Backplane Glue Logic, Legacy PCI / ISA Bus Interface Bridges, Embedded CPU Address Decoding & Chip-Select Generation, Replacing Multiple 74-Series Discrete Logic ICs, Power-Up Sequencing & Reset Distribution.
Industrial Control & Factory Automation
The EPM7160ELI84-20 is well-suited for industrial PLCs, motor-control boards, and factory-automation controllers requiring deterministic glue logic between microcontrollers, sensors, and actuators. Its 160 macrocells and 64 user I/Os provide ample capacity to consolidate multiple 74LS/74HC discrete-logic packages into a single reprogrammable device, simplifying BOM and PCB layout. The industrial -40C to +85C temperature rating enables deployment in uncontrolled factory-floor environments without derating. The 20 ns pin-to-pin delay delivers deterministic timing for safety-interlock logic and emergency-stop signal paths. The 5V tolerance and JTAG ISP allow in-field firmware updates via standard programming hardware without removing the board from service, reducing maintenance windows in 24/7 production lines.
Recommended
Telecommunications Backplane Glue Logic
Legacy telecommunications line cards, T1/E1 interface boards, and central-office switching equipment commonly use the EPM7160ELI84-20 for address decoding, interrupt steering, and bus-interface bridging. The 62.5 MHz maximum frequency and 20 ns tPD comfortably handle bus-cycle timing for 33 MHz PCI and proprietary backplane protocols at 5V logic levels. The 64 user I/Os can replace dozens of discrete 74FCT and 74ABT logic devices, freeing board area for higher-value signal-conditioning circuitry. EEPROM-based instant-on configuration eliminates the need for external boot PROMs, critical for telecom systems that must come up in a defined state after power restoration. JTAG boundary-scan testability per IEEE 1149.1 simplifies board-level test and field diagnostics.
Recommended
Legacy PCI / ISA Bus Interface Bridges
The EPM7160ELI84-20 is widely deployed as a PCI-to-local-bus bridge, ISA bus decoder, and interrupt controller in embedded x86 systems where its 5V-tolerant I/Os and 20 ns propagation delay match the legacy bus timing budgets. Designers use its 160 macrocells to implement bus-state machines, address-decoder PLAs, and wait-state generators that would otherwise require multiple PAL/GAL devices. The 5.0V core supply aligns with PCI 5V signaling and ISA bus levels, avoiding the need for level shifters. EEPROM non-volatility means the bridge logic is operational within microseconds of power-on, satisfying the PCI specification's bus-enumeration timing requirements. The 84-pin PLCC remains in production for legacy board-repair and obsolescence-management programs in industrial PCs and point-of-sale terminals.
Recommended
Embedded CPU Address Decoding & Chip-Select Generation
Embedded designs based on 80186, 68k, PowerPC, and ARM7 processors use the EPM7160ELI84-20 to generate chip-select signals, decode memory maps, and arbitrate shared bus peripherals. Its 160 macrocells and 64 I/Os can implement 8 to 16 independent chip-select decoders with individually programmable wait-state insertion. The deterministic 20 ns tPD delivers consistent chip-select timing regardless of input combinations, critical for zero-wait-state memory interfaces. The non-volatile EEPROM configuration means the memory map is locked-in at power-on without external boot logic, simplifying system bring-up. Industrial temperature grade supports embedded boards deployed in outdoor enclosures, vehicle controllers, and ruggedized military/aerospace subsystems.
Recommended
Replacing Multiple 74-Series Discrete Logic ICs
The EPM7160ELI84-20 is a classic BOM-reduction tool, replacing 10 to 20 discrete 74LS, 74HC, 74FCT, or 74ABT logic packages with a single programmable device in legacy PCBs. Each macrocell can implement a sum-of-products equation equivalent to a 74-series PAL/GAL, and the wide input gating (up to 36 inputs per macrocell in MAX 7000) supports complex combinatorial functions. The 5V VCC directly replaces 74LS/74HC designs without supply changes. JTAG ISP allows engineers to fix logic bugs, add features, or respin functionality without reworking the PCB - a key advantage for legacy products still in service but out of production. This application is especially valuable in aerospace, medical-device, and industrial-automation fields where board re-spins are expensive or require regulatory re-certification.
Recommended
Power-Up Sequencing & Reset Distribution
In multi-rail systems requiring careful power-up sequencing (ASICs, FPGAs, microcontrollers, and analog ICs), the EPM7160ELI84-20 provides deterministic sequencing logic that becomes active immediately upon VCC ramp thanks to its non-volatile EEPROM configuration. The device can monitor up to 64 input rails or enable signals, generate programmable delay chains via its macrocell flip-flops, and drive sequencing outputs with 20 ns precision. Compared to a sequencer IC, the EPM7160ELI84-20 allows full customization of timing, polarity, and dependencies without a separate firmware step. Industrial temperature rating and 5V tolerance suit it for ATX, telecom-shelf, and industrial-PC power architectures where 5V standby rails are standard.
Recommended
Recommended Products Summary
Engineering reference data for EPM7160ELI84-20 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM7160ELC84-20 | EPM7160ELC84-15 | EPM7160ELC84-12 | EPM7160SLC84-10 | EPM7160SLC84-6 |
|---|---|---|---|---|---|---|
| Package | 84-Pin PLCC | 84-Pin PLCC - same | 84-Pin PLCC - same | 84-Pin PLCC - same | 84-Pin PLCC - same | 84-Pin PLCC - same |
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Macrocells | 160 | 160 | 160 | 160 | 160 | 160 |
| Usable Gates | 3.2K | 3.2K | 3.2K | 3.2K | 3.2K | 3.2K |
| Pin-to-Pin Delay (tPD) | 20 ns | 20 ns (same) | 15 ns (faster) | 12 ns (faster) | 10 ns (faster) | 6 ns (much faster) |
| Max Operating Frequency | 62.5 MHz | 62.5 MHz | 76.9 MHz | 100 MHz | 100 MHz | 125 MHz |
| Operating Temperature | -40C to +85C (Industrial) | 0C to +70C (Commercial) | 0C to +70C (Commercial) | 0C to +70C (Commercial) | 0C to +70C (Commercial) | 0C to +70C (Commercial) |
| Supply Voltage (VCC) | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V |
| Family | MAX 7000 | MAX 7000 | MAX 7000 | MAX 7000 | MAX 7000S | MAX 7000S |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Industrial temperature grade at 5V (vs EPM7160ELC84-20)
- Higher logic capacity than MAX 7000S -6 parts in same package (vs EPM7128SLC84-6N)
- Non-volatile EEPROM vs SRAM-based FPGAs (vs Cyclone FPGAs)
Design Notes
The EPM7160ELI84-20 requires a stable 5.0V (4.75-5.25V) supply with sufficient decoupling. Place a 0.1uF ceramic decoupling capacitor as close as possible to each VCC pin (the 84-PLCC has multiple VCC/GND pairs distributed around the package), plus a single 10uF tantalum or aluminum bulk capacitor at the board entry point. The device's I/O pins source/sink up to 25 mA per pin (typical), so total VCC current can exceed 200 mA in heavily-loaded designs - verify your regulator has adequate headroom. Avoid placing the CPLD near high-current switching nodes (relays, motor drivers) to minimize supply-rail noise coupling into the 5V rail.
For 84-pin PLCC designs, use a PLCC socket (machine-pin or low-profile) to allow in-system programming and easy replacement of obsolete parts. Keep JTAG signals (TDI, TDO, TMS, TCK) accessible via a 2x5 0.1-inch header for ByteBlasterMV/USB-Blaster connection during development and field updates. Route JTAG traces away from high-speed switching signals and keep them under 6 inches to maintain signal integrity. For the 84-PLCC, the recommended land pattern is JEDEC MS-018 - follow this exactly to ensure socket compatibility. Add a ground plane beneath the device to provide low-impedance return paths for the high-speed I/O switching currents.
Estimated: When migrating from EPM7160ELI84-20 (industrial -40C to +85C) to EPM7160ELC84-20 (commercial 0C to +70C), confirm the target environment stays within the C-grade temperature range or the device lifetime will be severely reduced. Do not assume the MAX 7000 family is pin-compatible with MAX 7000S - bitstream files are not interchangeable even though packages match; recompile in Quartus for any -S variant. The 5V I/Os cannot directly drive 3.3V logic above their VIH level without level shifters or resistor dividers. When designing for new products in 2026, prefer MAX II (EPM240/570) or MAX V (5M80ZE64) for active lifecycle and lower power, reserving MAX 7000 for legacy board-repair applications.
Compliance Information
RoHS non-compliant per Arrow EPM7160ELI84-20 listing (legacy 5V MAX 7000 PLCC part contains lead-based solder finish). AEC-Q100 not qualified - this is a general-purpose CPLD, not an automotive-grade part. Reach compliance status not explicitly listed in the provided data.
