EPM7160ELC84-15 - MAX 7000 CPLD, 160 Macrocells, 15ns, 84-PLCC
부품 번호: EPM7160ELC84-15 ✗ 단종| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $8.5 | $8.50 |
| 10 | $7.85 | $78.50 |
| 100 | $7 | $700.00 |
| 300 | $6.59 | $1,977.00 |
| 1,000 | $5.95 | $5,950.00 |
EPM7160ELC84-15 개요
A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that sits between simple SPLDs/GALs and FPGAs in the programmable logic hierarchy. It uses a classic AND-OR (sum-of-products) macrocell fabric with on-chip EEPROM to retain configuration without external memory, executes logic deterministically with predictable timing, and is widely used for glue logic, bus interfacing, and state-machine replacement. The MAX 7000 family uses Altera's second-generation MAX architecture, which adds fast input registers, programmable interconnect, and four dedicated Logic Array Blocks (LABs) per device for deterministic, pin-locked timing.
Key features include 64 macrocells across 4 Logic Array Blocks, 36 usable I/O pins, 5.0-V in-system programmability via JTAG, an internal 3.3-V PCI-compliant output drive option, and a programmable power-saving mode that reduces typical Icc standby to a fraction of active current. The EPM7160ELC84-15 is offered in the 84-pin PLCC (J-lead) package, providing easy prototyping on traditional through-hole PLCC sockets and reliable surface-mount assembly on J-lead land patterns.
The architecture partitions logic into LABs, each containing 16 macrocells with a programmable AND array feeding a fixed OR term, a flip-flop, and product-term allocation. This produces consistent, jitter-free combinatorial and registered propagation delays ideal for address decoding, interrupt control, peripheral bridging, and synchronous state machines. The 15-ns pin-to-pin delay translates to a maximum counter frequency of 76.9 MHz at 5 V.
Typical applications include bus-interface and address decoding in legacy 5-V systems, peripheral glue logic replacement for discrete 74LS/74HC TTL, industrial control and instrumentation, telecommunications line cards, and military/aerospace systems requiring non-volatile EEPROM-based logic. The wide 5-V tolerance and JTAG ISP make it well suited for both new designs and long-life maintenance of installed equipment.
When designing with this part, ensure your supply is 5 V (the 'E' suffix indicates the 5-V commercial-temp variant). Drive unused I/O pins to a defined state through software to minimize Icc, and use the JTAG boundary-scan chain to simplify board test. Designers migrating from 74LS/74HC logic should target the macrocell-limited MAX 7000S variants (e.g. EPM7160SLC84-10) when in-system programmability is required.
드롭인 대체품: EPM7160ELC84-15 — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: EPM7160ELC84-15 (동일 폼 팩터 및 풋프린트) — 차이점: Package, Operating Temperature, RoHS Status, Mounting Type, In-System Programmability.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
EPM7160SLC84-10
✅ 드롭인✓ 재고 있음
$35.77 / 개
데이터시트 보기 →EPM7160SLC84-7
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
EPM7160SLC84-6
✅ 드롭인✓ 재고 있음
$15.86 / 개
데이터시트 보기 →EPM7160ELC84-12
✅ 드롭인✓ 재고 있음
$11.1 / 개
데이터시트 보기 →EPM7160ELC84-10
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
EPM7160ELI84-20
✅ 드롭인✓ 재고 있음
$11.1 / 개
데이터시트 보기 →EPM7160ELI84-10
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
EPM7160ELC84-15 최대 정격 & 전기적 특성
| Family | MAX 7000 |
| Product Type | CPLD - Complex Programmable Logic Device |
| Architecture | EEPROM-based, second-generation MAX |
| Usable Gates | 3,200 |
| Macrocells | 160 |
| Logic Array Blocks | 4 |
| Maximum I/O Pins | 36 |
| Pin-to-Pin Delay | 15 ns |
| Counter Frequency | 76.9 MHz |
| Supply Voltage (Vcc) | 5 V |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) |
| Package Type | 84-pin PLCC (J-Lead) |
| 실장 유형 | Surface Mount (PLCC socket compatible) |
| 동작 온도 | 0 C to +70 C (commercial) |
| RoHS 상태 | Contains lead / RoHS non-compliant (per Altera listing) |
EPM7160ELC84-15 핀 구성
| 핀 1 | I/O — User I/O pin (macrocell) |
| 핀 2 | I/O — User I/O pin (macrocell) |
| 핀 3 | I/O — User I/O pin (macrocell) |
| 핀 4 | I/O — User I/O pin (macrocell) |
| 핀 5 | I/O — User I/O pin (macrocell) |
| 핀 6 | I/O — User I/O pin (macrocell) |
| 핀 7 | GND — Ground |
| 핀 8 | I/O — User I/O pin (macrocell) |
| 핀 9 | I/O — User I/O pin (macrocell) |
| 핀 10 | I/O — User I/O pin (macrocell) |
| 핀 11 | I/O — User I/O pin (macrocell) |
| 핀 12 | I/O — User I/O pin (macrocell) |
| 핀 13 | I/O — User I/O pin (macrocell) |
| 핀 14 | GND — Ground |
| 핀 15 | I/O — User I/O pin (macrocell) |
| 핀 16 | I/O — User I/O pin (macrocell) |
| 핀 17 | I/O — User I/O pin (macrocell) |
| 핀 18 | I/O — User I/O pin (macrocell) |
| 핀 19 | I/O — User I/O pin (macrocell) |
| 핀 20 | GND — Ground |
| 핀 21 | I/O — User I/O pin (macrocell) |
| 핀 22 | I/O — User I/O pin (macrocell) |
| 핀 23 | I/O — User I/O pin (macrocell) |
| 핀 24 | I/O — User I/O pin (macrocell) |
| 핀 25 | GND — Ground |
| 핀 26 | I/O — User I/O pin (macrocell) |
| 핀 27 | I/O — User I/O pin (macrocell) |
| 핀 28 | I/O — User I/O pin (macrocell) |
| 핀 29 | I/O — User I/O pin (macrocell) |
| 핀 30 | I/O — User I/O pin (macrocell) |
| 핀 31 | GND — Ground |
| 핀 32 | I/O — User I/O pin (macrocell) |
| 핀 33 | I/O — User I/O pin (macrocell) |
| 핀 34 | I/O — User I/O pin (macrocell) |
| 핀 35 | I/O — User I/O pin (macrocell) |
| 핀 36 | I/O — User I/O pin (macrocell) |
| 핀 37 | GND — Ground |
| 핀 38 | I/O — User I/O pin (macrocell) |
| 핀 39 | I/O — User I/O pin (macrocell) |
| 핀 40 | I/O — User I/O pin (macrocell) |
| 핀 41 | I/O — User I/O pin (macrocell) |
| 핀 42 | I/O — User I/O pin (macrocell) |
| 핀 43 | GND — Ground |
| 핀 44 | I/O — User I/O pin (macrocell) |
| 핀 45 | I/O — User I/O pin (macrocell) |
| 핀 46 | I/O — User I/O pin (macrocell) |
| 핀 47 | I/O — User I/O pin (macrocell) |
| 핀 48 | I/O — User I/O pin (macrocell) |
| 핀 49 | GND — Ground |
| 핀 50 | I/O — User I/O pin (macrocell) |
| 핀 51 | I/O — User I/O pin (macrocell) |
| 핀 52 | I/O — User I/O pin (macrocell) |
| 핀 53 | I/O — User I/O pin (macrocell) |
| 핀 54 | I/O — User I/O pin (macrocell) |
| 핀 55 | GND — Ground |
| 핀 56 | I/O — User I/O pin (macrocell) |
| 핀 57 | I/O — User I/O pin (macrocell) |
| 핀 58 | I/O — User I/O pin (macrocell) |
| 핀 59 | I/O — User I/O pin (macrocell) |
| 핀 60 | I/O — User I/O pin (macrocell) |
| 핀 61 | GND — Ground |
| 핀 62 | INPUT/GCLK — Global clock / dedicated input pin |
| 핀 63 | INPUT/OE1 — Global output enable / dedicated input |
| 핀 64 | INPUT/OE2/GCLK2 — Secondary global clock / output enable / dedicated input |
| 핀 65 | TDI — JTAG Test Data In (MAX 7000S only) |
| 핀 66 | TMS — JTAG Test Mode Select (MAX 7000S only) |
| 핀 67 | TCK — JTAG Test Clock (MAX 7000S only) |
| 핀 68 | NC — Not connected (per datasheet) |
| 핀 69 | NC — Not connected (per datasheet) |
| 핀 70 | NC — Not connected (per datasheet) |
| 핀 71 | NC — Not connected (per datasheet) |
| 핀 72 | NC — Not connected (per datasheet) |
| 핀 73 | NC — Not connected (per datasheet) |
| 핀 74 | TDO — JTAG Test Data Out (MAX 7000S only) |
| 핀 75 | VCC — 5.0V supply |
| 핀 76 | VCC — 5.0V supply |
| 핀 77 | VCC — 5.0V supply |
| 핀 78 | VCC — 5.0V supply |
| 핀 79 | VCC — 5.0V supply |
| 핀 80 | VCC — 5.0V supply |
| 핀 81 | VCC — 5.0V supply |
| 핀 82 | VCC — 5.0V supply |
| 핀 83 | VCC — 5.0V supply |
| 핀 84 | VCC — 5.0V supply |
일반적인 애플리케이션
EPM7160ELC84-15 적합 용도: 6 애플리케이션s: Legacy 5V Bus Address Decoding, Glue Logic Replacement (74LS/74HC TTL Consolidation), Industrial Control and Instrumentation, Telecommunications Line Cards and Backplane Bridging, Military and Aerospace Long-Life Programs, Peripheral Bridging and Interface Adaptation.
Legacy 5V Bus Address Decoding
The EPM7160ELC84-15 fits legacy 5-V address decoding because it operates directly from a 5 V rail without level translation, and its 15 ns pin-to-pin delay comfortably meets ISA, VME, and STD-bus timing budgets. With 160 macrocells it can hold dozens of independent decode windows (chip-select, memory map, interrupt acknowledge), consolidating what previously required multiple 74LS138/688 PLD pairs onto one PLCC84 device.
추천
Glue Logic Replacement (74LS/74HC TTL Consolidation)
The EPM7160ELC84-15 is well-suited for replacing dozens of 74LS/74HC glue-logic packages because its 160 macrocells absorb SSI/MSI functions (decoders, muxes, latches, simple state machines) into a single PLCC84 device. The 5 V tolerance means it interfaces directly to legacy TTL outputs, and its deterministic 15 ns propagation delay preserves the timing relationships the original TTL design depended on, simplifying BOM and PCB rework.
추천
Industrial Control and Instrumentation
Industrial control and instrumentation uses the EPM7160ELC84-15 as the deterministic glue logic between microcontrollers, ADCs, DACs, display drivers, and motor-control peripherals. Its 5 V CMOS I/O is noise-tolerant on long cable runs, the 84-pin PLCC package withstands industrial thermal cycling, and 160 macrocells accommodate multi-channel state machines for sequential valve/relay control. The commercial 0-70 C grade suits cabinet-mounted equipment; use the -ELI84 industrial variant for harsher environments.
추천
Telecommunications Line Cards and Backplane Bridging
The EPM7160ELC84-15 suits telecom line cards and backplane bridging because its 160 macrocells absorb protocol-format conversion (HDB3/AMI/8B10B framing), clock-domain crossing, and bus-arbitration state machines in one non-volatile device. The 5 V tolerance is native to legacy T1/E1 line interfaces, and the 76.9 MHz counter frequency cleanly handles sub-100 MHz system clocks. JTAG boundary-scan on the MAX 7000S variant accelerates board-level fault isolation.
추천
Military and Aerospace Long-Life Programs
The EPM7160ELC84-15 remains in service for military and aerospace long-life programs because MAX 7000 CPLDs are non-volatile (EEPROM configuration is retained without external boot memory), deterministic in timing, and supported through Intel PSG's long-term product programs. The 84-pin PLCC package tolerates conformal coating and rework, and obsolete parts flow through franchised brokers with full traceability, which is essential for DO-254 and MIL-HDBK-454 compliance documentation.
추천
Peripheral Bridging and Interface Adaptation
The EPM7160ELC84-15 is well suited for peripheral bridging and interface adaptation (e.g. parallel-bus to SPI, ISA to memory-mapped peripheral, or async SRAM to synchronous controller). Its 160 macrocells hold wide datapath muxes, the 5 V I/O bank mates with 3.3 V devices through simple resistive dividers, and the 15 ns Tpd fits the timing requirements of 33 MHz peripheral buses without inserting wait states.
추천
추천 제품 요약
엔지니어링 참조 데이터: EPM7160ELC84-15 — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | EPM7160SLC84-10 | EPM7160SLC84-7 | EPM7160SLC84-6 | EPM7160ELC84-12 | EPM7160ELC84-10 | EPM7160ELI84-20 | EPM7160ELI84-10 |
|---|---|---|---|---|---|---|---|---|
| Brand | Intel (formerly Altera) | Intel | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 84-pin PLCC | 84-pin PLCC - same | 84-pin PLCC - same | 84-pin PLCC - same | 84-pin PLCC - same | 84-pin PLCC - same | 84-pin PLCC - same | 84-pin PLCC - same |
| Macrocells | 160 | 160 | 160 | 160 | 160 | 160 | 160 | 160 |
| Usable Gates | 3,200 | 3,200 | 3,200 | 3,200 | 3,200 | 3,200 | 3,200 | 3,200 |
| Pin-to-Pin Delay (Tpd) | 15 ns | 10 ns (-33%) | 7.5 ns (-50%) | 6 ns (-60%) | 12 ns (-20%) | 10 ns (-33%) | 20 ns (+33%) | 10 ns (-33%) |
| Counter Frequency (Fcnt) | 76.9 MHz | 100 MHz | 125 MHz | 151 MHz | 83.3 MHz | 100 MHz | 76.9 MHz | 100 MHz |
| Supply Voltage | 5.0 V | 5.0 V - same | 5.0 V - same | 5.0 V - same | 5.0 V - same | 5.0 V - same | 5.0 V - same | 5.0 V - same |
| Temperature Range | 0 C to +70 C (commercial) | 0 C to +70 C (commercial) | 0 C to +70 C (commercial) | 0 C to +70 C (commercial) | 0 C to +70 C (commercial) | 0 C to +70 C (commercial) | -40 C to +85 C (industrial) | -40 C to +85 C (industrial) |
| In-System Programming (JTAG) | No (MAX 7000E - parallel only) | Yes (MAX 7000S) | Yes (MAX 7000S) | Yes (MAX 7000S) | No | No | No | No |
주요 차별점
- Same PLCC84 footprint as MAX 7000S JTAG-ISP variants (vs EPM7160SLC84-10)
- Three speed-grade upgrades available in the same package (vs EPM7160SLC84-7 / EPM7160SLC84-6)
- Industrial-temperature variants available for harsher environments (vs EPM7160ELI84-10 / EPM7160ELI84-20)
설계 노트
Estimated: at Vcc = 5.0 V and a typical Icc of 250 mA (commercial, all I/O switching at 76.9 MHz), the EPM7160ELC84-15 dissipates approximately 1.25 W. Use a 4-layer PCB with a continuous ground plane under the PLCC and at least 8 Vcc/GND pin pairs decoupled with 0.1 uF X7R ceramic capacitors placed within 3 mm of each Vcc pin. Add one bulk 10 uF tantalum or aluminum polymer capacitor at the board supply entry. The 'E' (5-V) supply must be regulated within +/- 10% (4.5 V to 5.5 V); exceeding 5.5 V will stress the EEPROM cells and may corrupt configuration.
The 84-pin PLCC J-lead package requires a land pattern per JEDEC MS-018 with 1.27 mm pitch. Recommended reflow profile follows JEDEC J-STD-020 (peak 235 C for SnPb, since this part is lead-bearing). For prototype work, use a through-hole PLCC84 socket (e.g. 3M Textool) so devices can be reprogrammed and replaced. Place all decoupling capacitors on the same PCB side as the CPLD and route Vcc/GND pairs in parallel, never daisy-chained, to keep supply inductance below 1 nH per pin.
Common pitfalls: (1) Don't assume the EPM7160ELC84-15 has JTAG ISP - it is a MAX 7000E (parallel programmable) variant; for JTAG ISP choose the EPM7160SLC84-10 or faster SLC speed grades. (2) Don't exceed 7 mA per I/O DC sink/source or you will degrade the output Voh/Vol levels. (3) Configure all unused I/O pins as outputs driving low (per Altera Quartus / MAX+PLUS II defaults) to minimize Icc standby. (4) When migrating from 74LS/74HC, derate your worst-case propagation delay calculation by 10% to account for I/O buffer variation across temperature.
규정 준수 정보
Altera listing explicitly states 'Contains lead / RoHS non-compliant'. The MAX 7000 family is fabricated on a 5-V CMOS EEPROM process; not qualified to AEC-Q100 (automotive). REACH and conflict-minerals status not disclosed in available data.