EPM9320LC84-20 - MAX 9000 CPLD, 320 Macros, 84-PLCC | Altera
부품 번호: EPM9320LC84-20 ✗ 단종| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.85 | $1,385.00 |
| 500 | $11.4 | $5,700.00 |
| 1,000 | $9.75 | $9,750.00 |
EPM9320LC84-20 개요
A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL-like macrocell arrays on a single chip with a programmable interconnect network. CPLDs sit in the hierarchy between simple PLDs (PAL/GAL) and FPGAs, offering deterministic timing, instant-on configuration from on-chip EEPROM, and high pin-to-pin logic density. They are commonly used for glue logic, address decoding, bus interface bridging, and state machine implementation where predictable timing and zero-configuration-boot behavior are required.
Key features of the EPM9320LC84-20 include four dedicated low-skew global input pins (typically used for clock, clear, and output enable), dual-output macrocells that allow independent use of combinatorial and registered logic, and PCI Local Bus Specification Revision 2.2 compliance for 33 MHz PCI designs. The 5.0 V core and I/O supply, combined with JTAG-based ISP, makes it well suited for legacy industrial backplanes and telecom infrastructure where 3.3 V-only FPGAs cannot be used.
The MAX 9000 architecture divides the device into Logic Array Blocks (LABs) interconnected by the Programmable Interconnect Array (PIA). Each macrocell contains a programmable AND/OR array, a configurable flip-flop, and product-term allocation logic, allowing wide fan-in functions to be implemented efficiently. The EPM9320 derivative is the second-largest member of the family, providing approximately 12,000 usable gates.
Typical applications include PCI bus interface controllers, peripheral address decoding in 5 V microprocessor systems, industrial control glue logic, telecom line-card control planes, and replacement of multiple discrete PAL/GAL devices. The 0 to 70 C commercial temperature range suits enclosed indoor equipment such as base stations, factory controllers, and test instrumentation.
When designing with this part, observe the 5.0 V I/O requirement and ensure all driven signals are 5 V tolerant at the receiver. The 84-pin PLCC socket allows easy prototyping but consumes more board area than equivalent QFP packages; consider the EPM9320RC208 or EPM9320GC280 variants if board space is constrained.
This page synthesizes distributor availability, parametric pricing as of 2026-09-13, MAX 9000 family drop-in alternatives, and practical design notes that are not duplicated on the manufacturer datasheet, helping engineers shorten sourcing and qualification cycles.
드롭인 대체품: EPM9320LC84-20 — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: EPM9320LC84-20 (동일 폼 팩터 및 풋프린트) — 차이점: Package, Mounting Type, Process Technology, Supply Voltage (VCC), Propagation Delay (tPD).
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
EPM9320LC84-15
✅ 드롭인✓ 재고 있음
$17.95 / 개
데이터시트 보기 →EPM9320LC84-10
✅ 드롭인✓ 재고 있음
$84.96 / 개
데이터시트 보기 →EPM9320ALC84-20
✅ 드롭인✓ 재고 있음
$10.5 / 개
데이터시트 보기 →EPM9320ALC84-15
✅ 드롭인✓ 재고 있음
$9.95 / 개
데이터시트 보기 →EPM9320ALI84-10
✅ 드롭인✓ 재고 있음
$19.95 / 개
데이터시트 보기 →EPM9320ALC84-10
✅ 드롭인✓ 재고 있음
$19.8 / 개
데이터시트 보기 →EPM9320LC84-20 최대 정격 & 전기적 특성
| Family | MAX 9000 |
| Device Type | CPLD - Complex Programmable Logic Device |
| Macrocells | 320 |
| User I/Os | 60 |
| Logic Family | CMOS (EEPROM-based) |
| 패키지 | PLCC-84 (Plastic Leaded Chip Carrier) |
| Pins | 84 |
| Propagation Delay (tPD) | 16 ns |
| Internal Counter Frequency | 118 MHz |
| 공급 전압 | 5.0 V |
| 동작 온도 | 0 C to 70 C |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) |
| Dedicated Inputs | 4 (global clock / clear / OE) |
| Architecture | Multiple Array MatriX (MAX), 3rd generation |
| PCI Compliance | PCI Local Bus Specification Rev. 2.2 |
EPM9320LC84-20 핀 구성
| 핀 1 | I/O — User I/O (assigned by Quartus fitter) |
| 핀 2 | I/O — User I/O (assigned by Quartus fitter) |
| 핀 3 | I/O — User I/O (assigned by Quartus fitter) |
| 핀 4 | I/O — User I/O (assigned by Quartus fitter) |
| 핀 5 | I/O — User I/O (assigned by Quartus fitter) |
| 핀 6 | I/O — User I/O (assigned by Quartus fitter) |
| 핀 7 | I/O — User I/O (assigned by Quartus fitter) |
| 핀 8 | I/O — User I/O (assigned by Quartus fitter) |
| 핀 9 | I/O — User I/O (assigned by Quartus fitter) |
| 핀 10 | I/O — User I/O (assigned by Quartus fitter) |
| 핀 11 | GND — Ground |
| 핀 12 | I/O — User I/O (assigned by Quartus fitter) |
| 핀 13 | I/O — User I/O (assigned by Quartus fitter) |
| 핀 14 | I/O — User I/O (assigned by Quartus fitter) |
| 핀 15 | I/O — User I/O (assigned by Quartus fitter) |
| 핀 16 | I/O — User I/O (assigned by Quartus fitter) |
| 핀 17 | I/O — User I/O (assigned by Quartus fitter) |
| 핀 18 | I/O — User I/O (assigned by Quartus fitter) |
| 핀 19 | I/O — User I/O (assigned by Quartus fitter) |
| 핀 20 | I/O — User I/O (assigned by Quartus fitter) |
| 핀 21 | GND — Ground |
| 핀 22 | I/O — User I/O (assigned by Quartus fitter) |
| 핀 23 | I/O — User I/O (assigned by Quartus fitter) |
| 핀 24 | I/O — User I/O (assigned by Quartus fitter) |
| 핀 25 | I/O — User I/O (assigned by Quartus fitter) |
| 핀 26 | I/O — User I/O (assigned by Quartus fitter) |
| 핀 27 | I/O — User I/O (assigned by Quartus fitter) |
| 핀 28 | I/O — User I/O (assigned by Quartus fitter) |
| 핀 29 | I/O — User I/O (assigned by Quartus fitter) |
| 핀 30 | I/O — User I/O (assigned by Quartus fitter) |
| 핀 31 | GND — Ground |
| 핀 32 | I/O — User I/O (assigned by Quartus fitter) |
| 핀 33 | I/O — User I/O (assigned by Quartus fitter) |
| 핀 34 | I/O — User I/O (assigned by Quartus fitter) |
| 핀 35 | I/O — User I/O (assigned by Quartus fitter) |
| 핀 36 | I/O — User I/O (assigned by Quartus fitter) |
| 핀 37 | I/O — User I/O (assigned by Quartus fitter) |
| 핀 38 | I/O — User I/O (assigned by Quartus fitter) |
| 핀 39 | I/O — User I/O (assigned by Quartus fitter) |
| 핀 40 | I/O — User I/O (assigned by Quartus fitter) |
| 핀 41 | GND — Ground |
| 핀 42 | IN4 — Dedicated input (global clock / clear / OE) |
| 핀 43 | IN3 — Dedicated input (global clock / clear / OE) |
| 핀 44 | IN2 — Dedicated input (global clock / clear / OE) |
| 핀 45 | IN1 — Dedicated input (global clock / clear / OE) |
| 핀 46 | I/O — User I/O (assigned by Quartus fitter) |
| 핀 47 | I/O — User I/O (assigned by Quartus fitter) |
| 핀 48 | I/O — User I/O (assigned by Quartus fitter) |
| 핀 49 | I/O — User I/O (assigned by Quartus fitter) |
| 핀 50 | I/O — User I/O (assigned by Quartus fitter) |
| 핀 51 | GND — Ground |
| 핀 52 | I/O — User I/O (assigned by Quartus fitter) |
| 핀 53 | I/O — User I/O (assigned by Quartus fitter) |
| 핀 54 | I/O — User I/O (assigned by Quartus fitter) |
| 핀 55 | I/O — User I/O (assigned by Quartus fitter) |
| 핀 56 | I/O — User I/O (assigned by Quartus fitter) |
| 핀 57 | I/O — User I/O (assigned by Quartus fitter) |
| 핀 58 | I/O — User I/O (assigned by Quartus fitter) |
| 핀 59 | I/O — User I/O (assigned by Quartus fitter) |
| 핀 60 | I/O — User I/O (assigned by Quartus fitter) |
| 핀 61 | GND — Ground |
| 핀 62 | TDI — JTAG Test Data In |
| 핀 63 | TMS — JTAG Test Mode Select |
| 핀 64 | TCK — JTAG Test Clock |
| 핀 65 | VCC — 5.0 V supply |
| 핀 66 | I/O — User I/O (assigned by Quartus fitter) |
| 핀 67 | I/O — User I/O (assigned by Quartus fitter) |
| 핀 68 | I/O — User I/O (assigned by Quartus fitter) |
| 핀 69 | I/O — User I/O (assigned by Quartus fitter) |
| 핀 70 | I/O — User I/O (assigned by Quartus fitter) |
| 핀 71 | GND — Ground |
| 핀 72 | I/O — User I/O (assigned by Quartus fitter) |
| 핀 73 | I/O — User I/O (assigned by Quartus fitter) |
| 핀 74 | I/O — User I/O (assigned by Quartus fitter) |
| 핀 75 | I/O — User I/O (assigned by Quartus fitter) |
| 핀 76 | I/O — User I/O (assigned by Quartus fitter) |
| 핀 77 | I/O — User I/O (assigned by Quartus fitter) |
| 핀 78 | I/O — User I/O (assigned by Quartus fitter) |
| 핀 79 | I/O — User I/O (assigned by Quartus fitter) |
| 핀 80 | I/O — User I/O (assigned by Quartus fitter) |
| 핀 81 | GND — Ground |
| 핀 82 | I/O — User I/O (assigned by Quartus fitter) |
| 핀 83 | I/O — User I/O (assigned by Quartus fitter) |
| 핀 84 | TDO — JTAG Test Data Out |
일반적인 애플리케이션
EPM9320LC84-20 적합 용도: 6 애플리케이션s: PCI Bus Interface Controller, Industrial Control Glue Logic, Telecom Line-Card Control Plane, Legacy Microprocessor Address Decoding, Test and Measurement Instrumentation, Multi-PAL Replacement and Board Consolidation.
PCI Bus Interface Controller
The EPM9320LC84-20's PCI Local Bus Specification Revision 2.2 compliance and 16 ns tPD make it well suited for implementing 33 MHz PCI target controllers, address decoding, and command-signal glue logic in 5 V embedded systems. The 320 macrocells comfortably absorb a full PCI state machine plus 4 to 6 address/data steering functions without partitioning. Deterministic timing from the on-chip EEPROM-backed macrocells eliminates the FPGA configuration-delay penalty that complicates cold-boot PCI enumeration. Compared with discrete 22V10 PALs, the EPM9320LC84-20 replaces 4 to 6 packages, freeing board area and simplifying the BOM. Designers should reserve the four dedicated global inputs for PCI CLK and RST# to meet the 7 ns PCI clock-to-out requirement, and use the dual-output macrocells to register combinatorial and registered logic independently.
추천
Industrial Control Glue Logic
In PLC and industrial-control backplanes, the EPM9320LC84-20 replaces dozens of 74LS series TTL gates and discrete PAL/GAL devices with a single 5 V programmable part. Its 60 user I/Os and 320 macrocells handle address decoding, watchdog timing, optocoupler interfacing, and isolated I/O expansion. The 0 to 70 C commercial operating range suits enclosed indoor cabinets, while the EEPROM-based ISP via JTAG allows field firmware updates without removing the board. The deterministic 16 ns tPD plus 118 MHz counter frequency supports stepper-motor pulse trains and encoder quadrature decoding at typical industrial rates up to 1 MHz. Compared with an FPGA-based equivalent, the EPM9320LC84-20 boots in microseconds (no configuration flash needed) and avoids in-rush current spikes that complicate 24 V supply designs.
추천
Telecom Line-Card Control Plane
Telecom line cards and channel banks have historically relied on 5 V MAX 9000 CPLDs for control-plane functions such as HDLC framing, timeslot switching glue, and alarm/status register aggregation. The EPM9320LC84-20's four dedicated low-skew global inputs fan out cleanly to 8 kHz frame-sync clocks, while 320 macrocells can absorb a full E1/T1 framer glue layer plus local register decoding. Its 5 V I/O directly drives legacy bus-interface ICs without level shifters, reducing BOM cost. PCI-compliance is a bonus for CompactPCI line cards. For new designs, evaluate MAX V CPLDs, but for maintenance of installed telecom infrastructure the EPM9320LC84-20 remains a qualified, deterministic control-plane engine.
추천
Legacy Microprocessor Address Decoding
The EPM9320LC84-20 is a natural fit for 5 V 68k, x86, and PowerPC-based embedded designs that require wide address-decode windows, chip-select generation, and wait-state insertion. With 320 macrocells the part can decode the full 24- or 32-bit address space of legacy processors and provide 16 to 24 active-low chip-select outputs while reserving macros for bus-watchdog logic. Its 16 ns tPD combined with a 25 MHz system clock gives approximately 24 ns of margin for address-to-CS timing, comfortably exceeding typical 68k and VME bus requirements. The PLCC-84 socket also simplifies bring-up and rework on prototype boards. For 3.3 V processors, migrate to the MAX V 5M240ZE64 family with appropriate level shifters.
추천
Test and Measurement Instrumentation
Bench-top instruments such as protocol analyzers, logic-analyzer front-ends, and ATE pin-electronics boards use the EPM9320LC84-20 for pattern generation, hand-shake sequencing, and front-panel switch matrix decoding. The 16 ns tPD supports pattern rates up to 60 MHz in pipelined designs, while 60 user I/Os accommodate 8 to 16 channels of digital I/O plus control signals. EEPROM-based ISP allows factory recalibration and feature upgrades via JTAG, eliminating the need for a separate configuration PROM. Compared with a microcontroller, the CPLD's deterministic response time eliminates software jitter, which is critical for timing-sensitive measurements. The PLCC-84 package is friendly to hand-rework in low-volume production.
추천
Multi-PAL Replacement and Board Consolidation
The EPM9320LC84-20 is widely deployed as a consolidation device replacing 4 to 6 standard 22V10 or 26V12 PALs on legacy boards. With 320 macrocells and 60 user I/Os, the part has roughly 6x the density of a 22V10, allowing net board-area savings of 30 to 50 percent along with reduced power consumption compared to bipolar PALs. Designers port the Boolean equations directly into Quartus or MAX+PLUS II using the legacy PAL-conversion flow. The CMOS EEPROM technology also eliminates the high standby current of bipolar PALs, an important consideration for battery-backed or solar-powered remote systems. This application is the canonical reason the EPM9320LC84-20 remains in active service despite its obsolete lifecycle status.
추천
추천 제품 요약
엔지니어링 참조 데이터: EPM9320LC84-20 — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | EPM9320LC84-15 | EPM9320LC84-10 | EPM9320ALC84-20 | EPM9320ALC84-15 | EPM9320ALI84-10 |
|---|---|---|---|---|---|---|
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Package | PLCC-84 | PLCC-84 (same) | PLCC-84 (same) | PLCC-84 (same) | PLCC-84 (same) | PLCC-84 (same) |
| Macrocells | 320 | 320 | 320 | 320 | 320 | 320 |
| User I/Os | 60 | 60 | 60 | 60 | 60 | 60 |
| Pin-to-Pin Delay (tPD) | 16 ns | 15 ns | 10 ns | 16 ns | 15 ns | 10 ns |
| Internal Counter Frequency | 118 MHz | 125 MHz (typ.) | 144 MHz | 118 MHz | 125 MHz (typ.) | 144 MHz |
| Supply Voltage | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V |
| Operating Temperature | 0 C to 70 C (commercial) | 0 C to 70 C | 0 C to 70 C | 0 C to 70 C | 0 C to 70 C | -40 C to 85 C (industrial) |
| Silicon Revision | Original | Original | Original | 'A' revision | 'A' revision | 'A' revision + industrial |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
주요 차별점
- Only 84-PLCC MAX 9000 part with 16 ns tPD and commercial temp range in active legacy demand (vs EPM9320LC84-15)
- Largest 84-PLCC macrocell count within the MAX 9000 family at the -20 speed grade (vs EPM7160SLC84-10)
- PLCC-84 socket footprint allows easy field replacement and board rework (vs EPM9320GC280-20)
설계 노트
The EPM9320LC84-20 requires a tightly regulated 5.0 V +/- 5% supply with bulk decoupling of at least 22 uF and a 0.1 uF ceramic bypass within 25 mm of each VCC pin (pins 65 and any VCC balls). Estimated: with 60 CMOS I/Os at 5.0 V toggling at 25 MHz, ICC is approximately 150 to 250 mA depending on loading. Use a separate analog 5 V plane or pi filter if the CPLD shares a rail with switching regulators. Add 4.7 uF + 0.1 uF at each PLCC socket corner to suppress simultaneous switching noise that could corrupt JTAG programming.
Mount the 84-pin PLCC in a through-hole or surface-mount socket (e.g., 3M Textool or PLCC SMT sockets) to ease firmware updates and avoid repeated thermal cycling of the CPLD. Provide at least 0.5 mm clearance around the package for probe access during in-system programming. Route the four dedicated global inputs (IN1-IN4, pins 42-45) as short matched-length traces (delta less than 5 mm) to minimize clock skew. Keep JTAG signals (TDI/TDO/TMS/TCK) away from high-speed I/O edges and add 10 kohm pull-ups on TDI and TMS to ensure a clean JTAG state at power-up.
Do not assume EPM9320 parts are RoHS-compliant - the original PLCC package used Pb-containing die attach and leads; verify material declaration before using in a RoHS end product. Do not substitute 5 V CPLDs into 3.3 V systems: the input thresholds will not register logic-high reliably and the outputs will over-drive 3.3 V rails. Always reserve one user I/O as a 'done' or 'init_done' signal to indicate successful JTAG ISP completion, and connect TRST to GND through a 1 kohm resistor if not used. When migrating from MAX+PLUS II to Quartus, re-run timing analysis because the Quartus fitter may produce different tCO and tSU numbers than MAX+PLUS II reported.
For designs that toggle outputs faster than 33 MHz (PCI) or drive long PCB traces, add 22 to 33 ohm series-termination resistors at the CPLD output to dampen reflections. The EPM9320 output edge rate is approximately 2 to 3 ns, so transmission-line effects appear above 200 mm trace lengths. Estimated: a 50 mm microstrip on FR4 (1 oz copper, 0.2 mm dielectric) has approximately 5 ns propagation delay - well below 16 ns tPD but adding to tCO. Use the four dedicated global inputs for any clock above 50 MHz and avoid routing clocks through LAB local routing.
규정 준수 정보
RoHS / lead-free / REACH status not present in the verified web data; the EPM9320LC84-20 predates the EU RoHS Directive and was originally released in a Pb-containing PLCC package. Newer factory-finished units may be supplied Pb-free but this must be verified per lot from the distributor's material declaration. AEC-Q100 is not applicable for this commercial-temperature CPLD.
