EP910DI-35 vs EP910DM-40 Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EP910DI-35 disebabkan oleh Altera dan EP910DM-40 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Pengandingan Spesifikasi

Parametr EP910DI-35 EP910DM-40
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Aktif Obsolete
Product Type EPLD (Erasable Programmable Logic Device) UV Erasable Programmable Logic Device (EPLD)
Family Altera Classic EPLD Altera Classic EP910
Macrocells 24 24
Usable Gates 450 —
Propagation Delay (tPD) 35 ns 40 ns
Maximum Toggle Frequency (fCNT) 28.6 MHz —
Supply Voltage (VCC) 4.75 V to 5.25 V (5 V nominal) —
Supply Current (ICC) 40 mA typical —
Dedicated Inputs 10 36
Bidirectional I/O Pins 20 —
Total Pins 40 —
Kemasan CDIP-40 (Ceramic DIP with UV window) 40-pin Ceramic DIP (Cerdip) with UV window
Jenis Pemasangan Through-Hole Through-Hole (DIP)
Suhu Operasi -40C to +85C (industrial) [DATA_NEEDED: operating temperature range]
Technology CMOS, UV-erasable EPROM —
Programming Method EPROM programmer + JEDEC fuse map —
Erasure Method UV light through quartz window —
Status RoHS [DATA_NEEDED: RoHS status - ceramic CDIP legacy parts are typically non-compliant unless specified] [DATA_NEEDED: RoHS compliance status]
Logic Family PAL-type AND/OR array with D flip-flops —
Manufacturer Original Altera; long-term authorized by Rochester Electronics, LLC —
Architecture — PAL-type AND/OR with global programmable interconnect bus
Dedicated Outputs — 24
Bidirectional I/O Lines — 24
Product Terms — 240
External Clocks — 2
Process Technology — CMOS
Tegangan Pemberi Arus — 5 V
Programming Interface — JEDEC-standard fuse-map / UV erasure

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