EP910DI-35 vs EP910DM-40 对比
详细并排对比 EP910DI-35 出自 Altera 和 EP910DM-40 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP910DI-35 | EP910DM-40 |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 有效 | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $35.20 | $21.00 |
| Product Type | EPLD (Erasable Programmable Logic Device) | UV Erasable Programmable Logic Device (EPLD) |
| Family | Altera Classic EPLD | Altera Classic EP910 |
| Macrocells | 24 | 24 |
| Usable Gates | 450 | — |
| Propagation Delay (tPD) | 35 ns | 40 ns |
| Maximum Toggle Frequency (fCNT) | 28.6 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | — |
| Supply Current (ICC) | 40 mA typical | — |
| Dedicated Inputs | 10 | 36 |
| Bidirectional I/O Pins | 20 | — |
| Total Pins | 40 | — |
| 封装 | CDIP-40 (Ceramic DIP with UV window) | 40-pin Ceramic DIP (Cerdip) with UV window |
| 安装类型 | Through-Hole | Through-Hole (DIP) |
| 工作温度 | -40C to +85C (industrial) | [DATA_NEEDED: operating temperature range] |
| Technology | CMOS, UV-erasable EPROM | — |
| Programming Method | EPROM programmer + JEDEC fuse map | — |
| Erasure Method | UV light through quartz window | — |
| RoHS 状态 | [DATA_NEEDED: RoHS status - ceramic CDIP legacy parts are typically non-compliant unless specified] | [DATA_NEEDED: RoHS compliance status] |
| Logic Family | PAL-type AND/OR array with D flip-flops | — |
| Manufacturer | Original Altera; long-term authorized by Rochester Electronics, LLC | — |
| Architecture | — | PAL-type AND/OR with global programmable interconnect bus |
| Dedicated Outputs | — | 24 |
| Bidirectional I/O Lines | — | 24 |
| Product Terms | — | 240 |
| External Clocks | — | 2 |
| Process Technology | — | CMOS |
| 电源电压 | — | 5 V |
| Programming Interface | — | JEDEC-standard fuse-map / UV erasure |