EP910DI-35 vs EP910DM-40 比較
詳細並排比較 EP910DI-35 由 Altera 與 EP910DM-40 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP910DI-35 | EP910DM-40 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 啟用中 | Obsolete |
| Product Type | EPLD (Erasable Programmable Logic Device) | UV Erasable Programmable Logic Device (EPLD) |
| Family | Altera Classic EPLD | Altera Classic EP910 |
| Macrocells | 24 | 24 |
| Usable Gates | 450 | — |
| Propagation Delay (tPD) | 35 ns | 40 ns |
| Maximum Toggle Frequency (fCNT) | 28.6 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | — |
| Supply Current (ICC) | 40 mA typical | — |
| Dedicated Inputs | 10 | 36 |
| Bidirectional I/O Pins | 20 | — |
| Total Pins | 40 | — |
| 封裝 | CDIP-40 (Ceramic DIP with UV window) | 40-pin Ceramic DIP (Cerdip) with UV window |
| 安裝類型 | Through-Hole | Through-Hole (DIP) |
| 工作溫度 | -40C to +85C (industrial) | [DATA_NEEDED: operating temperature range] |
| Technology | CMOS, UV-erasable EPROM | — |
| Programming Method | EPROM programmer + JEDEC fuse map | — |
| Erasure Method | UV light through quartz window | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status - ceramic CDIP legacy parts are typically non-compliant unless specified] | [DATA_NEEDED: RoHS compliance status] |
| Logic Family | PAL-type AND/OR array with D flip-flops | — |
| Manufacturer | Original Altera; long-term authorized by Rochester Electronics, LLC | — |
| Architecture | — | PAL-type AND/OR with global programmable interconnect bus |
| Dedicated Outputs | — | 24 |
| Bidirectional I/O Lines | — | 24 |
| Product Terms | — | 240 |
| External Clocks | — | 2 |
| Process Technology | — | CMOS |
| 供應電壓 | — | 5 V |
| Programming Interface | — | JEDEC-standard fuse-map / UV erasure |