EP910DI-35 vs EP910DM-40 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP910DI-35 sa pamamagitan ng Altera at EP910DM-40 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP910DI-35 EP910DM-40
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Aktibo Obsolete
Product Type EPLD (Erasable Programmable Logic Device) UV Erasable Programmable Logic Device (EPLD)
Family Altera Classic EPLD Altera Classic EP910
Macrocells 24 24
Usable Gates 450 —
Propagation Delay (tPD) 35 ns 40 ns
Maximum Toggle Frequency (fCNT) 28.6 MHz —
Supply Voltage (VCC) 4.75 V to 5.25 V (5 V nominal) —
Supply Current (ICC) 40 mA typical —
Dedicated Inputs 10 36
Bidirectional I/O Pins 20 —
Total Pins 40 —
Packhaging CDIP-40 (Ceramic DIP with UV window) 40-pin Ceramic DIP (Cerdip) with UV window
Uri ng Pagpapasok Through-Hole Through-Hole (DIP)
Temperature na Operasyon -40C to +85C (industrial) [DATA_NEEDED: operating temperature range]
Technology CMOS, UV-erasable EPROM —
Programming Method EPROM programmer + JEDEC fuse map —
Erasure Method UV light through quartz window —
Tindminan RoHS [DATA_NEEDED: RoHS status - ceramic CDIP legacy parts are typically non-compliant unless specified] [DATA_NEEDED: RoHS compliance status]
Logic Family PAL-type AND/OR array with D flip-flops —
Manufacturer Original Altera; long-term authorized by Rochester Electronics, LLC —
Architecture — PAL-type AND/OR with global programmable interconnect bus
Dedicated Outputs — 24
Bidirectional I/O Lines — 24
Product Terms — 240
External Clocks — 2
Process Technology — CMOS
Volte ng Pagbibigay — 5 V
Programming Interface — JEDEC-standard fuse-map / UV erasure

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