10AX115S2F45E2LG - Arria 10 GX FPGA 1150K LE, 624 I/O | Altera
MPN: 10AX115S2F45E2LG ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $8500 | $8,500.00 |
| 10 | $8200 | $82,000.00 |
| 100 | $7800 | $780,000.00 |
| 250 | $7400 | $1,850,000.00 |
| 500 | $7100 | $3,550,000.00 |
Drop-in alternatives for 10AX115S2F45E2LG — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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10AX115S2F45E1SG
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$5650 / Unit
View Datasheet →10AX115S1F45I1SG
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View Datasheet →10AX115S1F45E1SG
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$5850 / Unit
View Datasheet →10AX115N2F45E2SG
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View Datasheet →10AX115H2F34E2LG
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View Datasheet →10AX115S2F45E2LG Maximum Ratings & Electrical Characteristics
| Family | Arria 10 GX |
| Logic Elements | 1,150,000 |
| Embedded Memory | 68,857,600 bits |
| User I/O Count | 624 |
| Process Technology | 20 nm |
| Core Voltage | 0.9 V |
| Package | 1932-ball FCBGA |
| Mounting Type | Surface Mount |
| Speed Grade | -2 (industrial) |
| Temperature Grade | E2 (extended) |
| Transceivers | Up to 28.05 Gbps (per family datasheet) |
| DSP Blocks | Hardened fixed/floating-point DSP blocks |
| Hard Memory Controllers | Yes (DDR4/QDRIV+ via soft IP) |
| PCIe Hard IP | PCIe Gen3/Gen4 capable |
| Configuration | Active Serial / Fast Passive Parallel |
| RoHS Status | Compliant |
10AX115S2F45E2LG Pin Configuration
| Pin 1 | BALL A1 — Multi-function user I/O / power / GND (see Arria 10 GX family pinout file) |
| Pin 2 | BALL A2 — Multi-function user I/O / power / GND (see Arria 10 GX family pinout file) |
| Pin 3 | BALL A3 — Multi-function user I/O / power / GND (see Arria 10 GX family pinout file) |
| Pin 1932 | BALL (last) — Multi-function user I/O / power / GND (see Arria 10 GX family pinout file) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
10AX115S2F45E2LG is suitable for 6 applications: 100G/400G Optical Transport, Software Defined Radio (SDR) Baseband, High Frame Rate Video Processing, ASIC Prototyping and Emulation, PCI Express Acceleration Card, Radar and Electronic Warfare.
100G/400G Optical Transport
The 10AX115S2F45E2LG fits 100G and 400G optical transport platforms because its 28.05 Gbps multi-gigabit transceivers and 1150K-LE fabric can process multiple lanes of 100G Ethernet, OTU4, or FlexE traffic simultaneously. The high transceiver count supports four 100G CFP/CFP2 links or sixteen 25G SFP28 channels without external muxing. Large embedded memory enables deep queueing for OTN framing and FEC processing on-chip, reducing external buffer cost and latency.
Recommended
Software Defined Radio (SDR) Baseband
The 10AX115S2F45E2LG fits SDR baseband processing because its hardened floating-point DSP blocks deliver deterministic throughput for FFT, channelization, and modulation/demodulation math. The 1,150,000 logic elements support multi-antenna MIMO processing, while the embedded 68 Mbit memory holds wide sample buffers and twiddle-factor tables on-chip. The extended temperature grade and FCBGA thermal mass make it suitable for outdoor or ruggedized radio enclosures used in defense and public-safety networks.
Recommended
High Frame Rate Video Processing
The 10AX115S2F45E2LG fits high frame-rate broadcast and pro-AV video pipelines because its 624 I/Os support multi-stream 12G-SDI or DisplayPort 1.4 ingest, while 68 Mbit of embedded memory enables line, frame, and chroma-format buffers without external SRAM. The fabric can host multiple parallel video processing pipelines (deinterlacing, scaling, color space conversion) concurrently. The 28.05 Gbps transceivers can also drive HDMI 2.1 / 8K transport links in production routers.
Recommended
ASIC Prototyping and Emulation
The 10AX115S2F45E2LG fits ASIC prototyping and emulation platforms because the 1,150,000-LE fabric can be partitioned into multiple ASIC clock domains and the hardened PCIe Gen3/Gen4 IP bridges to host CPU emulation engines. The 1932-ball FCBGA exposes enough high-speed transceivers and general-purpose I/Os to map large ASIC SoC pinouts for pre-silicon validation. Quartus Prime incremental compilation allows rapid bring-up of partitioned ASIC code, accelerating tape-out readiness for the target foundry node.
Recommended
PCI Express Acceleration Card
The 10AX115S2F45E2LG fits PCIe Gen3/Gen4 acceleration workloads because the hardened PCIe IP delivers up to 16 GT/s link bandwidth with low-latency DMA, and the 68 Mbit of embedded memory supports packet buffers and lookup tables on-chip. Designers can implement machine-learning inference, financial analytics, or storage compression accelerators with multiple parallel compute engines inside the fabric. The FCBGA package maintains signal integrity for the PCIe edge connector at full line rate.
Recommended
Radar and Electronic Warfare
The 10AX115S2F45E2LG fits radar and electronic-warfare signal processing because its hardened DSP blocks support pulse-Doppler, SAR, and digital beamforming math at deterministic throughput. The 28.05 Gbps transceivers accept raw ADC data from multiple antenna channels, while 68 Mbit of embedded memory holds range-Doppler maps and angle-of-arrival buffers. The extended temperature grade and high-reliability FCBGA packaging meet MIL-STD-810 vibration and thermal requirements for airborne and ground-mobile platforms.
Recommended
Recommended Products Summary
Engineering reference data for 10AX115S2F45E2LG — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10AX115S2F45E1SG | 10AX115S1F45I1SG | 10AX115S1F45E1SG | 10AX115N2F45E2SG | 10AX115H2F34E2LG |
|---|---|---|---|---|---|---|
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Package | 1932-ball FCBGA (F45) | 1932-ball FCBGA (F45) - same | 1932-ball FCBGA (F45) - same | 1932-ball FCBGA (F45) - same | 1932-ball FCBGA (F45) - same | 1932-ball FCBGA (F45) - same |
| Logic Elements | 1,150,000 | 1,150,000 | 1,150,000 | 1,150,000 | 1,150,000 | 1,150,000 |
| Embedded Memory | 68,857,600 bits | 68,857,600 bits | 68,857,600 bits | 68,857,600 bits | 68,857,600 bits | 68,857,600 bits |
| Speed Grade | -2 | -2 | -1 | -1 | -2 | -2 |
| Temperature Grade | E2 (extended) | E1 | I1 (industrial) | E1 | E2 | E2 |
| Transceiver Variant | GX (28.05 Gbps) | GX | GX | GX | No transceivers | High-speed variant |
| Core Voltage | 0.9 V | 0.9 V | 0.9 V | 0.9 V | 0.9 V | 0.9 V |
Key Differentiators
- Extended temperature grade E2 in same 1932-ball FCBGA package (vs 10AX115S2F45E1SG)
- Higher speed grade -2 for tighter timing margin (vs 10AX115S1F45E1SG)
- Full GX transceiver complement (vs 10AX115N2F45E2SG)
Design Notes
Estimated: The Arria 10 GX 1150K-LE device in the 1932-ball FCBGA package can dissipate 25-35 W in a typical 28 Gbps transceiver-heavy workload. The FCBGA exposes a large thermal lid that should be bonded to a heatsink or cold plate using a high-conductivity thermal interface material (1-3 W/m-K minimum). Without active cooling, the junction temperature can rise above 100 C in still air. Always simulate worst-case Tj using Intel's Arria 10 PowerPlay early in the design cycle to size the cooling solution accurately.
The 1932-ball FCBGA at 1 mm pitch requires a high-layer-count PCB (typically 14-22 layers) with microvia escape patterns following Intel's BGA escape guidelines. Use via-in-pad with copper-filled and capped microvias on the top layers for transceiver and high-speed signal breakout. Provide a continuous GND reference plane under the BGA and stitch vias around the periphery to suppress simultaneous-switching-noise on the GPIO banks. A symmetrical via array beneath the thermal pad is essential for heat transfer to internal copper planes.
Multi-gigabit transceivers operating at 28.05 Gbps require controlled-impedance routing (typically 85 ohm differential for transceivers, 50 ohm single-ended for GPIO), length matching within tight skew tolerances (often sub-ps), and DC-blocking capacitors at the transceiver pins. Use Intel's Arria 10 Transceiver Signal Integrity Toolkit and follow the IBIS-AMI flow for channel simulation. Insertion loss budget should be verified with 3D EM extraction before tape-out to avoid post-layout re-spins.
Do not confuse the Arria 10 device variants: S = GX (transceivers), N = no transceivers, R = RX (fewer transceivers), H = high-speed variant. Mixing these parts on the same PCB footprint may result in pinout differences in the transceiver banks. Also note that the F45 package designation is unique to the 1932-ball outline; do not assume F34/F40/F45 packages are interchangeable. Always verify the device variant and package code from the full orderable part number against the device pinout file before committing to PCB fabrication.
Compliance Information
RoHS and lead-free per Altera/Intel product page. AEC-Q100 is not applicable to FPGAs in this family (industrial temperature grade only).
