10AX115S2F45E2SG - Arria 10 GX 1.15M LE FPGA, 28.05 Gbps | Intel
MPN: 10AX115S2F45E2SG ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $8717.2 | $8,717.20 |
| 10 | $8281.34 | $82,813.40 |
| 100 | $7845.48 | $784,548.00 |
| 500 | $7410.62 | $3,705,310.00 |
| 1,000 | $6975.76 | $6,975,760.00 |
Drop-in alternatives for 10AX115S2F45E2SG — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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10AX115S2F45E2LG
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$7100 / Unit
View Datasheet →10AX115S2F45E1SG
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$5650 / Unit
View Datasheet →10AX115S1F45I1SG
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View Datasheet →10AX115S1F45E1SG
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$5850 / Unit
View Datasheet →10AX090S2F45E2SG
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$2050 / Unit
View Datasheet →10AX115S2F45E2SG Maximum Ratings & Electrical Characteristics
| Family | Arria 10 GX |
| Logic Elements (LE) | 1,150,000 |
| Adaptive Logic Modules (ALM) | 427,200 |
| Embedded Memory Bits | 68,857,856 |
| Embedded 18x19 Multipliers | 1,518 |
| Maximum User I/O Pins | 624 |
| Transceiver Count | 24 channels |
| Maximum Transceiver Data Rate | 28.05 Gbps |
| Process Technology | 20 nm TSMC |
| Core Voltage (Vcc) | 0.9 V (nominal) |
| Hard PCIe Gen3 Blocks | 2 |
| Fractional PLLs | 4 |
| I/O PLLs | 8 |
| Package | 1932-ball FC-FBGA (F45) |
| Mounting Type | Surface Mount |
| Operating Temperature Grade | E2 (0C to +100C) |
| RoHS Status | Compliant |
| Speed Grade | 2 (mid) |
10AX115S2F45E2SG 1932-ball fc-fbga (f45) Pin Configuration Guide
Complete pinout information for 10AX115S2F45E2SG (1932-ball fc-fbga (f45) package) with 624 pins. This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for 10AX115S2F45E2SG.
Refer to the datasheet for full pin configuration.
Estimated pin count: 624 pins (digital package)
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
10AX115S2F45E2SG is suitable for 6 applications: 100G OTN Optical Transport Line Cards, 4K Broadcast Video Processing and Display Walls, ASIC Prototyping in the Data Center, PCIe Gen3 Accelerator Cards, Radar and Electronic Warfare Signal Processing, 100G Ethernet MAC/PHY Bridging.
100G OTN Optical Transport Line Cards
The 10AX115S2F45E2SG is purpose-built for 100G OTN optical transport line cards thanks to its 24 transceivers at 28.05 Gbps, which natively drive OTU4 client-side optics and inter-card backplanes without external muxponders. The 1,150,000 LE fabric implements the full OTU4 framer, GFP-F mapper, and OTN FEC decoder, while the two hard PCIe Gen3 blocks offload traffic to co-located switch ASICs. With 1,518 18x19 multipliers, the device also handles real-time OTN performance monitoring and per-channel BER calculations concurrently with line-rate data forwarding.
Recommended
4K Broadcast Video Processing and Display Walls
The 10AX115S2F45E2SG's 1,150,000 LE fabric and 68,857,856 embedded memory bits make it a strong fit for 4K broadcast video processors that perform real-time scaling, deinterlacing, and color-space conversion across multiple 12G-SDI inputs. The 24 transceivers at 28.05 Gbps handle 12G-SDI (11.88 Gbps) and emerging 24G-SDI protocols over a single coax per channel, reducing connector count and PCB area. With 1,518 DSP multipliers, the device can also implement real-time HDR tone mapping and frame-rate conversion for live broadcast display walls and video wall controllers.
Recommended
ASIC Prototyping in the Data Center
The 10AX115S2F45E2SG serves as a mid-range ASIC prototyping platform in cloud data centers thanks to its 1,150,000 LE fabric that maps hundreds of millions of ASIC gates for pre-silicon validation. Designers partition ASIC RTL across multiple FPGAs using gigabit transceivers at 28.05 Gbps to wire up chip-to-chip communication, while the two hard PCIe Gen3 blocks interface directly to host server platforms for bring-up and regression testing. The 68,857,856 embedded memory bits approximate typical ASIC SRAM densities without requiring external memory controllers.
Recommended
PCIe Gen3 Accelerator Cards
The 10AX115S2F45E2SG integrates two hard PCIe Gen3 blocks that natively support x1, x2, x4, and x8 lane configurations, enabling direct deployment in PCIe Gen3 accelerator cards without external PHY silicon. Combined with 1,518 18x19 multipliers and 68,857,856 embedded memory bits, the device can host machine-learning inference engines, scientific computing kernels, or storage offload pipelines that benefit from FPGA-level parallelism. The 24 transceivers also support 10/25/40/100 GbE sideband networking for cluster-scale accelerator fabrics.
Recommended
Radar and Electronic Warfare Signal Processing
The 10AX115S2F45E2SG's 1,518 18x19 multipliers deliver 2,268 18x18 multiplications per cycle, enabling multi-channel radar FFT pipelines and digital-beamforming on a single device. The 24 transceivers at 28.05 Gbps digitize and forward ADC samples from phased-array antennas directly into the FPGA fabric, while the 1,150,000 LE fabric implements matched filtering, pulse compression, and constant-false-alarm-rate detection. With 68,857,856 embedded memory bits, the device holds multiple FFT windows in real time without external SRAM.
Recommended
100G Ethernet MAC/PHY Bridging
The 10AX115S2F45E2SG implements 100G Ethernet MAC plus PCS soft logic alongside the integrated 28.05 Gbps transceivers, enabling direct interface to 100G QSFP28 optical modules without external MAC/PHY silicon. The two hard PCIe Gen3 blocks can simultaneously bridge to host CPUs, turning the device into a 100G NIC or smart-NIC offload engine. The 1,150,000 LE fabric adds headroom for inline packet processing, telemetry, or wire-speed encryption alongside the 100G data path.
Recommended
Recommended Products Summary
Engineering reference data for 10AX115S2F45E2SG — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10AX115S2F45E2LG | 10AX115S2F45E1SG | 10AX115S1F45I1SG | 10AX115S1F45E1SG | 10AX090S2F45E2SG |
|---|---|---|---|---|---|---|
| Package | 1932-ball FC-FBGA (F45) | 1932-ball FC-FBGA (F45) - same | 1932-ball FC-FBGA (F45) - same | 1932-ball FC-FBGA (F45) - same | 1932-ball FC-FBGA (F45) - same | 1932-ball FC-FBGA (F45) - same |
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Logic Elements | 1,150,000 | 1,150,000 | 1,150,000 | 1,150,000 | 1,150,000 | 900,000 (-22%) |
| Max Transceiver Data Rate | 28.05 Gbps | 28.05 Gbps | 28.05 Gbps | 17.4 Gbps (-38%) | 17.4 Gbps (-38%) | 28.05 Gbps |
| Speed Grade | -2 (mid) | -2 | -1 (slower) | -1 | -1 | -2 |
| Temperature Grade | E2 (0C to +100C) | E2 | E1 (0C to +100C, lower speed) | I1 (-40C to +100C industrial) | E1 | E2 |
| Lead Finish | Lead-free (G) | Leaded (L) | Lead-free (G) | Lead-free (G) | Lead-free (G) | Lead-free (G) |
| Embedded 18x19 Multipliers | 1,518 | 1,518 | 1,518 | 1,518 | 1,518 | 1,048 (-31%) |
Key Differentiators
- Highest transceiver data rate in the 115K LE Arria 10 GX family at this speed grade (vs 10AX115S2F45E1SG)
- Highest logic density in the F45 Arria 10 GX package at 28.05 Gbps (vs 10AX090S2F45E2SG)
- Lead-free (RoHS-compliant) lead finish by default (vs 10AX115S2F45E2LG)
Design Notes
Estimated: at 28.05 Gbps per channel, route all 24 transceiver lanes as 100-ohm differential pairs on the top microstrip or stripline layer with matched length to within 0.127 mm (5 mil) intra-pair and 6.4 mm inter-pair. Place AC-coupling capacitors within 3 mm of the FPGA ball, keep the ground plane unbroken under transceiver routes, and use a continuous reference return path. Intel's Arria 10 GX Transceiver User Guide documents the specific via-in-pad rules and loss budget that the F45 package requires.
Estimated: at 0.9 V core and full fabric utilization on the 1,150,000 LE Arria 10 device, supply current can exceed 30 A during peak switching activity. Design a low-impedance 0.9 V VRM using 4-6 parallel phases with ceramic bulk capacitance of at least 2,200 uF on the supply plane, and place decoupling capacitors (100 nF, 10 nF, 1 nF) within 1.5 mm of every Vcc ball. Use Intel's PowerPlay early power estimator in Quartus Prime to size the VRM before schematic capture.
Estimated: the 1932-ball FC-FBGA F45 package has a theta-JA of approximately 6 C/W with top-side air cooling, which means 20 W of dissipation raises the junction by 120 C above ambient. For forced-air cooled telecom designs, attach a heat spreader with thermal interface material (TIM) rated for at least 3 W/mK to the top of the package and ensure 200 LFM airflow. Run the Arria 10 junction-temperature estimation in Quartus Prime to verify thermal margin before committing the PCB stackup.
Estimated: a common pitfall in Arria 10 GX designs is forgetting the 1.8 V or 2.5 V VCCIO bank supply for general-purpose I/O pins, which is independent from the 0.9 V core supply and must be sequenced per Intel's Arria 10 GX Power Management User Guide. Another pitfall is using LVDS signals without enabling the on-chip LVDS serializer/deserializer block in Quartus Prime Pin Planner. Always verify pin assignments against the F45 ball-grid map and run the Quartus Prime I/O Assignment Analysis before generating programming files.
Compliance Information
RoHS compliance per Intel Arria 10 GX product page (lead-free 'G' suffix). Lead-free finish designates RoHS-compliant termination. Not AEC-Q100 qualified - FPGAs are not subject to automotive stress-test qualification. Conflict-minerals statement available via Intel corporate compliance program.
