10AX115S3F45E2LG - Arria 10 GX 1150K LE FPGA | Intel | 1932-FCBGA
MPN: 10AX115S3F45E2LG β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $8928.97 | $8,928.97 |
| 10 | $8710 | $87,100.00 |
| 100 | $8450 | $845,000.00 |
| 500 | $8200 | $4,100,000.00 |
| 1,000 | $7950 | $7,950,000.00 |
Drop-in alternatives for 10AX115S3F45E2LG β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
10AX115S3F45E2SG
β Drop-Inβ In Stock
$6200 / Unit
View Datasheet β10AX115S3F45E1SG
β Drop-Inπ Reference alternative (not in catalog)
10AX115S3F45I1SG
β Drop-Inπ Reference alternative (not in catalog)
10AX115S2F45E2LG
β Drop-Inβ In Stock
$7100 / Unit
View Datasheet β10AX115S2F45E2SG
β Drop-Inβ In Stock
$6975.76 / Unit
View Datasheet β10AX115S3F45I2SG
β Drop-Inβ In Stock
$2020 / Unit
View Datasheet β10AX115S3F45E2LG Maximum Ratings & Electrical Characteristics
| Family | Arria 10 GX |
| Logic Elements | 1,150,000 |
| Embedded Memory | 68,857,856 bits |
| User I/O | 624 |
| Core Voltage | 0.9 V |
| Process Technology | 20 nm |
| Package | 1932-BBGA, FCBGA |
| Footprint | F45 |
| Speed Grade | -2 (Extended) |
| Temperature Grade | Extended |
| Transceivers | Up to 28.05 Gbps backplane-capable |
| DSP Blocks | Hardened floating-point DSP |
| PCIe Hard IP | PCIe Gen3 x8 hard IP |
| Lead-Free / RoHS | Yes (lead-free finish, RoHS compliant) |
| Mounting Type | Surface Mount (BGA) |
10AX115S3F45E2LG Pin Configuration
| Pin 1 | IO_xxx β User I/O ball; refer to Quartus Prime pin planner for exact ball coordinates in the F45 footprint |
| Pin 2 | IO_xxx β User I/O ball; refer to Quartus Prime pin planner for exact ball coordinates in the F45 footprint |
| Pin 3 | IO_xxx β User I/O ball; refer to Quartus Prime pin planner for exact ball coordinates in the F45 footprint |
| Pin 4 | IO_xxx β User I/O ball; refer to Quartus Prime pin planner for exact ball coordinates in the F45 footprint |
| Pin 5 | IO_xxx β User I/O ball; refer to Quartus Prime pin planner for exact ball coordinates in the F45 footprint |
| Pin 6 | IO_xxx β User I/O ball; refer to Quartus Prime pin planner for exact ball coordinates in the F45 footprint |
| Pin 7 | IO_xxx β User I/O ball; refer to Quartus Prime pin planner for exact ball coordinates in the F45 footprint |
| Pin 8 | IO_xxx β User I/O ball; refer to Quartus Prime pin planner for exact ball coordinates in the F45 footprint |
| Pin 9 | IO_xxx β User I/O ball; refer to Quartus Prime pin planner for exact ball coordinates in the F45 footprint |
| Pin 10 | IO_xxx β User I/O ball; refer to Quartus Prime pin planner for exact ball coordinates in the F45 footprint |
| Pin 11 | IO_xxx β User I/O ball; refer to Quartus Prime pin planner for exact ball coordinates in the F45 footprint |
| Pin 12 | IO_xxx β User I/O ball; refer to Quartus Prime pin planner for exact ball coordinates in the F45 footprint |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
10AX115S3F45E2LG is suitable for 6 applications: High-Speed Video Broadcast and Processing, Medical Imaging and Diagnostic Equipment, Test and Measurement Instrumentation, Wireless Baseband Pre-Processing, Defense and Aerospace Signal Processing, Industrial Control and High-Speed Data Acquisition.
High-Speed Video Broadcast and Processing
The 10AX115S3F45E2LG fits 4K/8K video broadcast and processing because its 1,150,000 logic elements and embedded DSP blocks can sustain multi-stream HEVC/AVC pipelines at full frame rate, while the 28.05 Gbps transceivers carry uncompressed video over SMPTE ST 2082 (12G-SDI) links. Designers place the device on a multi-layer PCB with matched-length SDI traces and route the transceiver channels through AC-coupled connectors to preserve signal integrity at 12 Gbps. Compared with a discrete CPU+GPU stack, the Arria 10 GX delivers deterministic latency and lower per-frame jitter, which is critical for live broadcast timing.
Recommended
Medical Imaging and Diagnostic Equipment
The 10AX115S3F45E2LG suits medical imaging because its hardened floating-point DSP slices accelerate CT, MRI, and ultrasound reconstruction kernels (filtered back-projection, beamforming) in deterministic cycles. The Extended temperature grade supports the thermal envelope inside an imaging cabinet, and the 68,857,856 bits of embedded memory hold image-line buffers close to the logic, cutting external DRAM round-trips. Engineers typically pair it with a JESD204B ADC front end, clocked from the FPGA's transceiver PLLs, and stream samples into on-chip memory for real-time processing at frame rates above 30 fps.
Recommended
Test and Measurement Instrumentation
The 10AX115S3F45E2LG is widely deployed in oscilloscopes, logic analyzers, and protocol testers because its 624 user I/O plus 28.05 Gbps transceivers handle multi-channel analog front-end capture and PCIe Gen3 host upload in parallel. The high logic density supports deep on-chip acquisition memory and real-time trigger logic at sample rates above 5 GSPS, while the PCIe hard IP block offloads waveform data to the host CPU without tying up transceiver resources. Designers use the FPGA's partial-reconfiguration feature to swap between protocol analyzer personalities (PCIe, USB, Ethernet) in the field.
Recommended
Wireless Baseband Pre-Processing
The 10AX115S3F45E2LG supports wireless baseband pre-processing because its hardened DSP and CPRI/OBSAI-capable transceivers handle multi-antenna radio front-haul at up to 9.8 Gbps per channel. The 1,150,000 logic elements implement crest-factor reduction (CFR) and digital pre-distortion (DPD) engines that linearize power amplifiers in 4G/5G small-cell radios. Engineers typically pair the FPGA with a host SoC over PCIe Gen3 and run the pre-processing pipeline at line rate without loading the SoC, preserving headroom for stack-layer processing.
Recommended
Defense and Aerospace Signal Processing
The 10AX115S3F45E2LG meets defense signal-processing needs because its Extended temperature range, hardened DSP blocks, and high logic capacity allow radar pulse compression, electronic-warfare channelization, and SIGINT demodulation in a single device. Designers implement polyphase filter banks and FFT engines on-chip and stream processed data via the 28.05 Gbps transceivers to a downstream recorder or display processor. Compared with a discrete DSP cluster, the Arria 10 GX reduces SWaP-C by collapsing multiple boards into one BGA, an important advantage in size-constrained platforms.
Recommended
Industrial Control and High-Speed Data Acquisition
The 10AX115S3F45E2LG is well suited to industrial data acquisition because its 624 user I/O and high-density logic can interface with parallel ADC/DAC banks, while the transceivers serialize the resulting streams to a host controller. Designers implement deterministic real-time control loops in the FPGA fabric, bypassing the jitter of a CPU-based PLC, and use partial reconfiguration to switch between sensor configurations on the line. Compared with a microcontroller stack, the Arria 10 GX gives deterministic sub-microsecond loop times and deterministic GPIO-to-transceiver latency.
Recommended
Recommended Products Summary
Engineering reference data for 10AX115S3F45E2LG β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10AX115S3F45E2SG | 10AX115S3F45E1SG | 10AX115S3F45I1SG | 10AX115S2F45E2LG |
|---|---|---|---|---|---|
| Package | 1932-BBGA FCBGA (F45) | 1932-BBGA FCBGA (F45) - same | 1932-BBGA FCBGA (F45) - same | 1932-BBGA FCBGA (F45) - same | 1932-BBGA FCBGA (F45) - same |
| Brand | Intel | Intel | Intel | Intel | Intel |
| Speed Grade | -2 (Extended) | -2 (Extended) | -1 (Extended) | -1 (Industrial) | -2 (Extended) |
| Temperature Grade | Extended | Extended | Extended | Industrial | Extended |
| Lead-Free Finish | Yes (RoHS) | No (non-RoHS finish) | No (non-RoHS finish) | No (non-RoHS finish) | Yes (RoHS) |
| Logic Elements | 1,150,000 | 1,150,000 | 1,150,000 | 1,150,000 | 1,150,000 |
| Embedded Memory | 68,857,856 bits | 68,857,856 bits | 68,857,856 bits | 68,857,856 bits | 68,857,856 bits |
| User I/O | 624 | 624 | 624 | 624 | 624 |
| Transceiver Class | S3 (highest transceiver count) | S3 (same) | S3 (same) | S3 (same) | S2 (reduced transceivers) |
| Approx. Unit Price (qty 1) | $8,928.97 | Similar (~$8,500-$9,000) | Higher (~$9,500-$10,500) | Higher (~$10,000-$11,000) | Lower (~$7,500-$8,500) |
Key Differentiators
- Lead-free, RoHS-compliant Extended-temperature grade (vs 10AX115S3F45E2SG)
- Speed grade -2 for lower cost vs -1 (vs 10AX115S3F45E1SG)
- Highest transceiver class (S3) in the 10AX115 family (vs 10AX115S2F45E2LG)
Design Notes
The Arria 10 GX device requires multiple voltage rails (0.9 V core, 1.1 V auxiliary, 1.8 V I/O, plus transceiver rails). Power-on sequencing is mandatory per the Arria 10 datasheet: bring up the 1.8 V rail before the 0.9 V core, and respect the monotonic-rising requirement. Use the Intel-supplied PowerTree Designer tool and reference the Arria 10 GX Device Design Guidelines for sequencing and ramp-rate values.
For 28.05 Gbps backplane operation, the PCB stackup must be a low-loss material (e.g., Megtron 6 or equivalent) with controlled-impedance 100-ohm differential channels and continuous reference planes. Per Intel's Arria 10 Transceiver PHY User Guide, transceiver channels must use AC coupling and matched lengths within the lane-to-lane skew budget; violations will close the eye at 28 Gbps.
At full transceiver utilization the Arria 10 GX 1150K-LE part can dissipate 20-30 W. The 1932-ball FCBGA requires a properly designed heatsink or cold plate with thermal interface material rated for the package. Reference the Arria 10 Thermal Management User Guide and use the junction-to-ambient thermal resistance from the device datasheet to size the cooling solution.
Do not assume the 10AX115S3F45E2LG and a non-LE Arria 10 device are interchangeable: the LE suffix denotes the standard logic-to-transceiver ratio, while the non-LE variants have fewer transceivers. Mixing them will cause Quartus Prime fitter errors and uncorrected pin mismatches. Always confirm the full MPN (10AX115S3F45E2LG, with the 'S3' transceiver code) matches the device order code in the BOM.
Compliance Information
RoHS-compliant lead-free finish per Intel product page; the LG suffix denotes lead-free per Arria 10 ordering information. AEC-Q100 not applicable for FPGAs.