5CGXBC9E6F35C7N - Cyclone V GX FPGA, 301K LE, 35C7 Speed | Intel
MPN: 5CGXBC9E6F35C7N β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $215 | $215.00 |
| 10 | $198.5 | $1,985.00 |
| 100 | $178 | $17,800.00 |
| 250 | $168.4 | $42,100.00 |
| 500 | $159.9 | $79,950.00 |
Drop-in alternatives for 5CGXBC9E6F35C7N β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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5CGXBC9E7F35C7N
β Drop-Inπ Reference alternative (not in catalog)
5CGXBC9E7F35C8N
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$555.1 / Unit
View Datasheet β5CGXBC9D7F35C8N
β Drop-Inπ Reference alternative (not in catalog)
5CGXBC9D6F35C7N
β Drop-Inπ Reference alternative (not in catalog)
5CGXFC9E7F35C7N
β Drop-Inπ Reference alternative (not in catalog)
5CGXBC9E6F35C7N Maximum Ratings & Electrical Characteristics
| Family | Cyclone V GX |
| Logic Elements | 301,000 |
| Embedded Memory (bits) | 14,251,008 |
| Total RAM (M20K + MLAB) | 9.45 Mbits |
| Embedded 18x18 Multipliers | 560 |
| Process Node | 28 nm |
| Core Voltage | 1.1 V |
| Speed Grade | 7 |
| Package | 1152-ball FBGA |
| User I/O Count | 364 (max for package) |
| Transceiver Channels | 9 (GTX, up to 3.125 Gbps) |
| PLL Count | 4 (fractional) |
| PCIe Hard IP | Gen2 (x1/x2/x4 lanes) |
| Configuration Modes | PS, FPP, JTAG |
| Operating Temperature | 0C to +85C (commercial) |
| RoHS Status | Compliant |
5CGXBC9E6F35C7N 1152-ball fbga Pin Configuration Guide
Complete pinout information for 5CGXBC9E6F35C7N (1152-ball fbga package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for 5CGXBC9E6F35C7N.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
5CGXBC9E6F35C7N is suitable for 6 applications: Industrial Machine Vision, Motor Control and Servo Drives, Low-Cost PCIe Endpoint Cards, Protocol Bridging and Industrial Networking, Small-Cell Wireless Backhaul, Video Broadcast and Image Processing.
Industrial Machine Vision
The 5CGXBC9E6F35C7N fits industrial machine vision pipelines because its 560 18x18 multipliers and 9.45 Mbits of embedded M20K memory handle Bayer demosaicing, edge detection, and histogram accumulation in real time at 1080p60. The 364 user I/O pins connect parallel image sensors, while 3.125 Gbps GTX channels stream processed frames to a host CPU over PCIe Gen2 or CoaXPress. Compared with a discrete DSP + FPGA design, the integrated PCIe hard IP cuts BOM cost by eliminating an external bridge chip, and Quartus Prime DSP Builder accelerates image-processing IP development.
Recommended
Motor Control and Servo Drives
The 5CGXBC9E6F35C7N integrates the DSP resources, encoder interfaces, and fieldbus controllers needed for a single-chip industrial servo drive. Its 560 18x18 multipliers run field-oriented control loops well under 1 microsecond, while 364 GPIO handle quadrature encoders, Hall sensors, and PWM outputs. The 9 GTX channels carry EtherCAT or PROFINET over MII/RGMII bridges, and 9.45 Mbits of embedded memory hold sinusoidal and SVM lookup tables. Industrial designers value the 0C to +85C commercial range and pin-compatible extended-temp variants for harsh cabinet environments.
Recommended
Low-Cost PCIe Endpoint Cards
The 5CGXBC9E6F35C7N ships with PCIe Gen2 hard IP that supports x1, x2, and x4 lanes, eliminating external bridge chips and reducing board cost for low-cost data acquisition cards, software-defined radio peripherals, and instrumentation. Its 9 GTX channels add USB 3.0, SATA, or multi-gigabit serial links alongside the PCIe connection, and 301K logic elements accommodate custom DMA engines, on-card buffering, and protocol logic. Designers pair it with the Intel Cyclone V PCIe development kit to shorten prototype cycles.
Recommended
Protocol Bridging and Industrial Networking
The 5CGXBC9E6F35C7N's combination of 3.125 Gbps transceivers and 364 GPIO makes it a flexible bridge between legacy industrial buses (PROFIBUS, RS-485, parallel TTL) and modern Ethernet protocols. Its 301K logic elements implement EtherCAT, PROFINET IRT, or EtherNet/IP slave stacks with hardware acceleration, while the embedded M20K blocks absorb network buffering. Compared with discrete PHY-plus-MCU solutions, the integrated transceiver approach reduces BOM by 30-40% and simplifies EMC compliance for factory-floor deployments.
Recommended
Small-Cell Wireless Backhaul
Small-cell base stations and remote-radio-head designs use the 5CGXBC9E6F35C7N for CPRI or OBSAI fronthaul aggregation over the 9 GTX channels at up to 3.125 Gbps each. The 560 18x18 multipliers implement Crest Factor Reduction and Digital Pre-Distortion algorithms to linearize power amplifiers, while 9.45 Mbits of embedded memory buffers IQ samples between the antenna and baseband. The 28 nm low-power Cyclone V architecture reduces thermal dissipation in outdoor sealed enclosures.
Recommended
Video Broadcast and Image Processing
Broadcast routers, video walls, and image-processing appliances use the 5CGXBC9E6F35C7N for multi-format video scaling, color-space conversion, and chroma keying. The 9 GTX channels carry 3G-SDI or DisplayPort streams at up to 3.125 Gbps per link, while 560 multipliers perform real-time 4:4:4 to 4:2:2 conversion. 9.45 Mbits of embedded memory holds multiple line buffers and lookup tables for LUT-based color grading, and the F35 364-pin GPIO count interfaces HDMI, DVI, and parallel RGB panels.
Recommended
Recommended Products Summary
Engineering reference data for 5CGXBC9E6F35C7N β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 5CGXBC9E7F35C7N | 5CGXBC9E7F35C8N | 5CGXBC9D7F35C8N | 5CGXBC9D6F35C7N | 5CGXFC9E7F35C7N |
|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 1152-ball FBGA (F35) | 1152-ball FBGA (F35) - same | 1152-ball FBGA (F35) - same | 1152-ball FBGA (F35) - same | 1152-ball FBGA (F35) - same | 1152-ball FBGA (F35) - same |
| Logic Elements | 301,000 | 301,000 | 301,000 | 301,000 | 301,000 | 301,000 |
| Embedded Memory (bits) | 14,251,008 | 14,251,008 | 14,251,008 | 14,251,008 | 14,251,008 | 14,251,008 |
| Embedded 18x18 Multipliers | 560 | 560 | 560 | 560 | 560 | 560 |
| Transceiver Channels / Max Rate | 9 GTX @ 3.125 Gbps | 9 GTX @ 3.125 Gbps | 9 GTX @ 3.125 Gbps | 9 GTX @ 3.125 Gbps | 9 GTX @ 3.125 Gbps | 9 GT @ 5 Gbps |
| PCIe Hard IP | Gen2 (x1/x2/x4) | Gen2 (x1/x2/x4) | Gen2 (x1/x2/x4) | Gen2 (x1/x2/x4) | Gen2 (x1/x2/x4) | Gen2 (x1/x2/x4) |
| Speed Grade | 7 (commercial) | 7 (industrial) | 8 (commercial) | 8 (industrial) | 7 (industrial) | 7 (industrial) |
| User I/O (Package Max) | 364 | 364 | 364 | 364 | 364 | 364 |
Key Differentiators
- Speed-grade 7 commercial timing closure for cost-sensitive designs (vs 5CGXBC9E7F35C8N)
- Lower-cost E-grade transceivers vs higher-end GT family (vs 5CGXFC9E7F35C7N)
- Largest F35 FBGA for maximum I/O in same family (vs 5CGXBC9E6F31C7N)
Design Notes
The 5CGXBC9E6F35C7N requires four separate supply rails - 1.1V core (VCC), 2.5V analog PLL (VCCA_PLL), 1.5V/1.8V/2.5V/3.3V bank I/O (VCCIO), and a 1.5V/1.8V transceiver supply (VCCH_GXB). Each rail should have a 100 uF bulk capacitor plus 0.1 uF and 0.01 uF ceramic bypass capacitors placed within 100 mil of every pin; Intel's Cyclone V hardware reference manual recommends a star-ground layout with the regulator sense line returning to the FPGA ground pin directly.
Estimated at full transceiver utilization with 3.125 Gbps PRBS-31 traffic on all 9 GTX channels, the F35 1152-ball FBGA junction-to-ambient thermal resistance (theta_JA) of approximately 12 C/W on a 4-layer JEDEC board yields 4.8 C rise per watt. For applications dissipating above 4W, a heatsink or forced-air cooling is recommended. The Cyclone V device handbook (CV-5V2) provides per-package theta_JB and theta_JC values for board-level thermal modeling.
The 1152-ball F35 FBGA uses a 1.0 mm ball pitch requiring microvia or staggered-via PCB fabrication with at least 6 routing layers for full breakout. Intel's Cyclone V pin connection guidelines specify matched-length trace routing for the GTX channels within 150 mil of each other plus 100-ohm differential impedance; reference clock lines must be length-matched to the clock input within 50 mil to preserve jitter budget at 3.125 Gbps.
Do not leave unused GTX transceiver channels floating - they must be powered down through the Quartus Prime device programming file (XCVR_TX_DISABLED / XCVR_RX_DISABLED). Unused M20K memory blocks can be left unconfigured but should be enabled in the fitter to minimize power. Always include external JTAG pull-ups (10 kohm to VCCIO of bank 3) and a 4.7 kohm pull-down on nCONFIG if using passive serial configuration.
Compliance Information
RoHS and lead-free per Intel product family datasheet; AEC-Q100 is not applicable for FPGAs (use AEC-Q100-qualified companion parts for automotive-grade designs).
