A42MX16-1PLG84 - 24K Gate FPGA, 84-PLCC | Microchip
MPN: A42MX16-1PLG84 β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $68.5 | $68.50 |
| 10 | $62.1 | $621.00 |
| 100 | $55.9 | $5,590.00 |
| 500 | $49.8 | $24,900.00 |
| 1,000 | $44.2 | $44,200.00 |
Drop-in alternatives for A42MX16-1PLG84 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
A42MX16-1PLG84I
β Drop-Inβ In Stock
$1 / Unit
View Datasheet βA42MX16-1PLG84M
β Drop-Inπ Reference alternative (not in catalog)
A42MX16-FPLG84
β Drop-Inβ In Stock
$21.5 / Unit
View Datasheet βA42MX16-1PLG84X39
β Drop-Inπ Reference alternative (not in catalog)
A42MX16-1PLG84MX39
β Drop-Inπ Reference alternative (not in catalog)
A42MX16-1PLG84 Maximum Ratings & Electrical Characteristics
| System Gates | 24,000 |
| Logic Cells | 608 |
| Family | 42MX (MX FPGA) |
| Process Technology | 0.45 um CMOS antifuse |
| Internal Frequency | 108 MHz (family rated 119 MHz/198 MHz) |
| Package Type | 84-pin PLCC (PLG84), plastic LCC |
| Pins | 84 |
| User I/O (package) | 72 programmable I/O lines |
| Max User I/O (family) | 202 |
| Dual-Port SRAM | Up to 2.5 kbits configurable |
| Supply Voltage (core/IO) | 3.0 V to 3.6 V and 4.75 V to 5.25 V |
| Logic Family | CMOS |
| Operating Temperature | -40C to +85C |
| Programming Technology | One-time programmable antifuse |
| Configuration | Non-volatile, no external boot ROM required |
| Mounting Type | Surface Mount |
| RoHS Status | [DATA_NEEDED: RoHS status] |
A42MX16-1PLG84 Pin Configuration
| Pin 1 | IO β User-programmable I/O (PLG84 assignments per DS2316 package table) |
| Pin 11 | VDD β Core supply (3.0-3.6V) - verify exact pin map in DS2316 |
| Pin 12 | GND β Ground |
| Pin 20 | VDDI β I/O supply (4.75-5.25V) - verify exact pin map in DS2316 |
| Pin 33 | CLK β Dedicated/global clock input |
| Pin 44 | TDI β JTAG boundary-scan data in / programming input |
| Pin 45 | TDO β JTAG boundary-scan data out |
| Pin 46 | TMS β JTAG test mode select |
| Pin 47 | TCK β JTAG test clock |
| Pin 84 | IO β User-programmable I/O |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
A42MX16-1PLG84 is suitable for 6 applications: Legacy PLD Consolidation, Industrial 5V Control Systems, Aerospace and Defense Subsystems, ASIC Prototyping and Bridge Logic, Test and Measurement Fixtures, Communications and Networking Glue Logic.
Legacy PLD Consolidation
The MX family is explicitly positioned by Microchip as a platform for integrating multiple legacy PLDs and CPLDs into a single low-cost 5V device. The A42MX16's 24,000 gates and 608 logic cells absorb several 22V10-class PLDs or small CPLDs at once, cutting board area, inventory SKUs, and assembly cost. Because the antifuse fabric is non-volatile, no configuration flash is needed - the consolidated design is simply programmed once and functions at power-up, preserving the deterministic behavior of the legacy logic it replaces.
Recommended
Industrial 5V Control Systems
With dual 3.0-3.6V and 4.75-5.25V supply support and 5V-tolerant I/O, the A42MX16-1PLG84 drops directly into existing 5V industrial backplanes and motor-control boards that modern SRAM FPGAs cannot interface with without level shifters. The 72 available I/O on the 84-PLCC drives relays, sensors, and optocouplers at 5V logic levels, while -40C to +85C operation covers unconditioned factory environments. The 108 MHz internal frequency is ample for state machines, sequencers, and encoder-processing logic in these systems.
Recommended
Aerospace and Defense Subsystems
Microsemi (now Microchip) antifuse FPGAs are traditional choices in defense and aerospace designs where configuration security matters: the antifuse bitstream cannot be read back, protecting design IP against extraction. The A42MX16-1PLG84M military-grade sibling supports extended temperature builds in the same 84-PLCC footprint. One-time programmability also eliminates the single-event configuration-upset failure mode of SRAM FPGAs in radiation environments, a key reliability argument for mission-critical glue logic and bus-interface functions.
Recommended
ASIC Prototyping and Bridge Logic
The MX family serves as a single-chip ASIC alternative for mid-volume products where mask ASIC NRE is uneconomical. Designers implement address decoders, bus bridges, wait-state generators, and custom peripheral interfaces in the 24K-gate fabric, using up to 2.5 kbits of configurable dual-port SRAM for FIFOs and scratch buffers. The wide-decode circuitry accelerates address comparison logic. Compared to discrete glue-logic builds, a single A42MX16 replaces dozens of SSI/MSI packages, improving timing closure at up to 108 MHz internal clock rates.
Recommended
Test and Measurement Fixtures
Production test fixtures and bench instruments benefit from the A42MX16's instant-on, no-boot behavior: programmed once, the device is active at power-up with no configuration delay, so test sequences start deterministically. The JTAG boundary-scan chain (TDI/TDO/TMS/TCK) supports board-level interconnect testing per the DS2316 datasheet, simplifying fixture self-test. The 5V I/O directly interfaces with legacy UUT test points, and the PLCC package can be socketed for reuse across fixture revisions without desoldering.
Recommended
Communications and Networking Glue Logic
In legacy telecom and networking line cards, the A42MX16 implements framing logic, clock-domain crossing bridges, and interrupt controllers between processors and PHY devices. The dual-port SRAM supports small FIFOs for rate adaptation between 5V legacy backplanes and 3.3V peripheral ICs. Designers value the low static power of the antifuse fabric in always-on chassis equipment, and the one-time-programmed configuration avoids the configuration-corruption concerns of SRAM FPGAs in long-uptime carrier equipment.
Recommended
Recommended Products Summary
Engineering reference data for A42MX16-1PLG84 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | A42MX16-1PLG84I | A42MX16-1PLG84M | A42MX16-FPLG84 | A42MX16-1PQG100 |
|---|---|---|---|---|---|
| Package | 84-PLCC (PLG84) | 84-PLCC - same | 84-PLCC - same | 84-PLCC - same (green) | 100-PQFP - different |
| Brand | Microchip Technology (Microsemi) | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| System Gates | 24,000 | 24,000 | 24,000 | 24,000 | 24,000 |
| Logic Cells | 608 | 608 | 608 | 608 | 608 |
| Temperature Grade | Commercial (0C to +70C) [DATA_NEEDED: confirm] | -40C to +85C industrial | Military grade | [DATA_NEEDED] | [DATA_NEEDED] |
| User I/O | 72 | 72 | 72 | 72 | [DATA_NEEDED: higher, PQFP100] |
| Supply Voltage | 3.0-3.6V / 4.75-5.25V | 3.0-3.6V / 4.75-5.25V | 3.0-3.6V / 4.75-5.25V | 3.0-3.6V / 4.75-5.25V | 3.0-3.6V / 4.75-5.25V |
| Internal Frequency | 108 MHz | 108 MHz | 108 MHz | 108 MHz | 108 MHz |
| Drop-in Compatible | - | Yes | Yes | Yes | No (different package) |
Key Differentiators
- Non-volatile antifuse configuration with no boot ROM (vs XC4000-class SRAM FPGAs)
- Configuration security (vs SRAM FPGAs)
- 5V-tolerant dual-rail I/O (vs A42MX16-1PQG100)
Design Notes
The 84-PLCC J-leaded package supports both solder mounting and low-cost PLCC sockets. If the design may need future die swaps (I vs M temperature grades), use a socket to allow field-grade changes. Follow the DS2316 mechanical drawing for land pattern dimensions; J-leads require allowance for lead spring during reflow.
The A42MX16 requires dual supplies: 3.0-3.6V (core, VDD) and 4.75-5.25V (I/O, VDDI). Sequence-free by design, but decouple both rails with 0.1uF ceramic caps per supply pin plus bulk 10uF per rail. Antifuse devices draw minimal static current, so rail sizing is dominated by dynamic I/O switching current.
This is a one-time-programmable antifuse FPGA: the design cannot be changed after programming. Complete full functional simulation, timing analysis, and pin-map verification in Libero SoC before programming. Reserve spare I/O on the 84-PLCC for ECO logic since the 72-I/O budget fills quickly in glue-logic consolidation projects.
Compliance Information
Abacus Technologies lists EU RoHS/REACH compliance for this family, but per-date-code verification with Microchip is required. The A42MX16-FPLG84 'F' variant is the green/lead-free packaging option. Not AEC-Q100 qualified.
