A42MX24-3PLG84 - 36K Gate MX FPGA, 84-PLCC | Microchip
MPN: A42MX24-3PLG84 β Last Time Buy| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $68.5 | $68.50 |
| 10 | $62.1 | $621.00 |
| 100 | $55.4 | $5,540.00 |
| 500 | $49.8 | $24,900.00 |
| 1,000 | $44.2 | $44,200.00 |
Drop-in alternatives for A42MX24-3PLG84 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
A42MX16-3PLG84
β Drop-Inβ In Stock
$1 / Unit
View Datasheet βA42MX16-2PLG84I
β Drop-Inβ In Stock
$30.8 / Unit
View Datasheet βA42MX16-1PLG84
β Drop-Inβ In Stock
$44.2 / Unit
View Datasheet βA42MX16-FPLG84
β Drop-Inβ In Stock
$21.5 / Unit
View Datasheet βA42MX36-3PLG84
β Drop-Inπ Reference alternative (not in catalog)
A42MX24-3PLG84I
β Drop-Inβ In Stock
$43.5 / Unit
View Datasheet βA42MX24-3PLG84 Maximum Ratings & Electrical Characteristics
| Family | MX (42MX) |
| System Gates | 36000 gates |
| Logic Cells | 912 |
| User I/O | 72 |
| Speed Grade | -3 (fastest commercial) |
| Supply Voltage (Core) | 3 V to 3.6 V |
| Supply Voltage (I/O) | 4.75 V to 5.25 V |
| Process Technology | 0.45 um |
| Package | 84-PLCC (J-Lead), 29.31 x 29.31 mm |
| Mounting Type | Surface Mount |
| Operating Temperature | 0C to +70C (TA) |
| Programmability | Antifuse (non-volatile) |
| Packaging | Tray |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Yes |
| Manufacturer Lead Time | 10 weeks |
| Product Status | Last Time Buy |
A42MX24-3PLG84 Pin Configuration
| Pin 1 | IO β User input/output (5V-tolerant, PLG84 pin assignment per DS2136) |
| Pin 10 | VCC β Core supply, 3.0V to 3.6V |
| Pin 21 | GND β Ground |
| Pin 22 | VCI β I/O supply, 4.75V to 5.25V |
| Pin 31 | TCK β JTAG test clock |
| Pin 32 | TDI β JTAG test data in |
| Pin 42 | TDO β JTAG test data out |
| Pin 43 | TMS β JTAG test mode select |
| Pin 52 | IO β User input/output |
| Pin 63 | IO β User input/output |
| Pin 73 | CLK β Dedicated clock input |
| Pin 84 | IO/GND β User I/O or ground pin per DS2136 pinout table |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
A42MX24-3PLG84 is suitable for 6 applications: Legacy PLD Integration, Industrial Control and Automation, Single-Chip ASIC Alternative, 5V-Tolerant Bus Interfacing, Defense and Aerospace Legacy Upgrades, Test and Measurement Equipment.
Legacy PLD Integration
The MX family was explicitly designed to consolidate multiple legacy PLDs, GALs, and 22V10-class devices into a single low-cost chip. The A42MX24's 36K gates and 912 cells provide ample capacity for several mid-size PLD functions, while its 5V-tolerant I/O directly interfaces with the 5V buses these legacy parts typically occupy. Because the antifuse fabric is non-volatile, no configuration PROM or microcontroller boot logic is needed, simplifying the upgrade path. D-modules provide wide-decode AND functions that efficiently replace the wide-input product-term structures of older CPLDs.
Recommended
Industrial Control and Automation
In industrial controllers, the A42MX24-3PLG84 implements state machines, I/O expansion, and bus glue logic with deterministic timing from the antifuse fabric. The dual-rail 3.3V core / 5V I/O arrangement lets it bridge modern 3.3V controllers to legacy 5V sensors and actuators without level shifters on up to 72 I/O pins. The 84-PLCC through-style J-lead package is field-serviceable from a socket, an advantage in repairable industrial equipment. Note the 0C to +70C commercial range limits use to conditioned environments; use the -I industrial variant for extended temperature.
Recommended
Single-Chip ASIC Alternative
Microchip positions MX FPGAs as a reliable single-chip ASIC alternative for medium-volume products where ASIC NRE is unjustifiable. The A42MX24 offers 36,000 system gates of one-time-programmable logic with full programming security - antifuse bits cannot be read back, protecting IP better than SRAM FPGAs. The -3 speed grade delivers the fastest MX timing for demanding glueless interfaces. Compared with mask ASICs, the MX approach has zero NRE, weeks-not-months turnaround, and survives the obsolescence of the A42MX24 via lifetime buys.
Recommended
5V-Tolerant Bus Interfacing
The A42MX24's 5.0V-tolerant I/O architecture makes it a natural bridge between 3.3V and 5V logic domains. With 72 user I/O powered from a 4.75-5.25V rail, it can directly receive 5V TTL signals while its 3.3V core keeps internal power low. Typical uses include VME/ISA-style backplane interfaces, 5V memory bus translation, and interfacing to legacy microprocessors. Designers should confirm per-bank current limits and add series termination on backplane lines; the datasheet DS2136 provides I OH/I OL and timing specs for the -3 grade under 5V conditions.
Recommended
Defense and Aerospace Legacy Upgrades
Antifuse FPGAs are favored in defense upgrade programs because they are immune to configuration upset and resistant to radiation-induced bit flips compared to SRAM fabrics. Programs that standardized on Actel MX silicon continue to use the A42MX24 for obsolescence-driven redesigns, weapon-system sustainment, and avionics retrofits where re-qualification of a new FPGA family is prohibitively expensive. The Last Time Buy status makes lifetime procurement planning essential; Microchip and distributors such as Microchip USA support end-of-life buy schedules for such programs.
Recommended
Test and Measurement Equipment
Bench and rack instruments use the A42MX24 for deterministic timing chains, trigger logic, and interface translation where the fixed routing delays of antifuse fabric provide repeatable skew performance unavailable in reprogrammable SRAM FPGAs. The 72 I/O and wide-decode D-modules implement fast address decoders and comparison logic with CPLD-like speed. The socketed 84-PLCC package simplifies field firmware behavior changes (a new programmed device can be swapped in). Commercial 0-70C rating suits laboratory environments typical of T&M deployments.
Recommended
Recommended Products Summary
Engineering reference data for A42MX24-3PLG84 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | A42MX16-3PLG84 | A42MX16-2PLG84I | A42MX16-1PLG84 | A42MX16-FPLG84 | A42MX36-3PLG84 |
|---|---|---|---|---|---|---|
| Package | 84-PLCC (J-Lead), 29.31x29.31 mm | 84-PLCC (J-Lead) - same | 84-PLCC (J-Lead) - same | 84-PLCC (J-Lead) - same | 84-PLCC (J-Lead) - same | 84-PLCC (J-Lead) - same |
| Brand | Microchip Technology (Microsemi/Actel MX) | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| System Gates | 36,000 | 16,000 | 16,000 | 16,000 | 16,000 | 36,000-54,000 |
| Logic Cells | 912 | [DATA_NEEDED: ~588 cells] | [DATA_NEEDED: ~588 cells] | [DATA_NEEDED: ~588 cells] | [DATA_NEEDED: ~588 cells] | [DATA_NEEDED] |
| User I/O | 72 | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
| Speed Grade | -3 (fastest) | -3 | -2 | -1 | F (standard) | -3 |
| Operating Temperature | 0C to +70C | 0C to +70C | -40C to +85C (industrial) | 0C to +70C | 0C to +70C | 0C to +70C |
| Lifecycle Status | Last Time Buy | Active/limited | Active/limited | Active/limited | Active/limited | Last Time Buy/limited |
Key Differentiators
- Largest capacity in the PLCC-84 MX footprint (vs A42MX16-3PLG84)
- Fastest MX timing bin (vs A42MX16-2PLG84I)
- 5V-tolerant non-volatile antifuse fabric (vs Cross-brand SRAM FPGAs (Xilinx/Intel))
Design Notes
The A42MX24-3PLG84 requires two independent rails: 3.0-3.6V core (VCC) and 4.75-5.25V I/O (VCI). Power the core rail before or simultaneously with the I/O rail. Decouple each rail with 0.1 uF ceramic capacitors at every supply pin plus bulk 10 uF. Antifuse devices draw negligible static current, so thermal design is dominated by I/O switching, not core logic.
MX devices are one-time-programmable: a programming error cannot be corrected in-system. Verify the design in simulation and, where possible, on a larger MX device before committing antifuse programming. Also note Last Time Buy status - secure program files, programmer availability (Silicon Sculptor), and spare programmed devices for the product lifetime.
The 84-PLCC J-lead package suits socketed field-serviceable boards but has higher lead inductance than QFP/BGA alternatives. For clocked designs near the -3 grade timing limits, keep clock traces short, use a dedicated clock input pin, and add series damping resistance (22-33 ohm) on fast output lines to control ringing from PLCC lead inductance.
The 5V I/O rail drives fast edges into backplane or cable loads. Add series termination at the FPGA output for point-to-point lines longer than ~10 cm, and confirm datasheet I OL/I OH budgets (DS2136) when bussing many loads. Unused I/O should be configured as inputs with pull-downs per the datasheet guidance.
Compliance Information
ROHS3 Compliant per Microchip USA distributor product page. AEC-Q100 qualification data not found in provided sources; an automotive-grade 40MX/42MX datasheet exists, but qualification status of this specific ordering code is unverified.
