DSPIC33CK64MP105-I/M4 - 100MHz DSC, 64KB Flash, 48-UQFN | Microchip
MPN: DSPIC33CK64MP105-I/M4 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $5.62 | $5.62 |
| 10 | $5.05 | $50.50 |
| 100 | $4.49 | $449.00 |
| 500 | $4.06 | $2,030.00 |
| 1,000 | $3.68 | $3,680.00 |
DSPIC33CK64MP105-I/M4 Overview
A digital signal controller combines the computational capability of a microcontroller with the DSP acceleration of a digital signal processor. Within the power-management hierarchy of embedded control ICs, DSCs sit between general-purpose MCUs and dedicated DSPs, offering a modified Harvard 16-bit architecture, DSP instruction support, and deterministic closed-loop control peripherals. The dsPIC33CK family is Microchip's single-core generation of this architecture, complementing the dual-core dsPIC33CH family.
Key features of the DSPIC33CK64MP105-I/M4 include the 100 MHz core executing up to 100 MIPS, 64 KB Flash with live self-programming, 8 KB SRAM, three integrated op amps for current-sense amplification, 12-bit high-speed ADC peripherals for simultaneous multi-channel sampling, comparators, and configurable MCCP/SCCP timer modules that can operate as PWM generators (up to six outputs per MCCP), input captures, output compares, or 16/32-bit timers. The I/O complement provides 39 GPIO with I2C, I2S, SPI and UART serial interfaces.
Architecturally, the CPU uses a 16-bit modified Harvard core with an enhanced instruction set including significant DSP support: a barrel shifter, dual operand fetch, and multiply-accumulate (MAC) operations. Four DMA channels move data between peripherals and RAM without CPU intervention, which is essential for high-bandwidth ADC sampling in digital power loops.
Typical applications include digital power supplies (LLC, totem-pole PFC), brushless DC and PMSM motor control with Field Oriented Control, advanced sensing front-ends, and co-processor roles alongside a host MCU.
Design consideration: the UQFN-48 exposed-pad package requires a solid ground connection via the thermal pad to the PCB; the internal VCAP regulator capacitor must be placed per the manufacturer datasheet guidelines for stable core operation.
This page synthesizes distributor pricing, drop-in family alternatives, and practical design notes not found in the manufacturer datasheet.
Drop-in alternatives for DSPIC33CK64MP105-I/M4 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with DSPIC33CK64MP105-I/M4 (same form factor and footprint) — differing in Core, Operating Temperature, PWM, Packaging, Supply Voltage.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
DSPIC33CK64MP105-H/M4
✅ Drop-In📋 Reference alternative (not in catalog)
DSPIC33CK64MC105T-I/M4
✅ Drop-In ⚠️ Specs Unverified✓ In Stock
Contact for price
View Datasheet →DSPIC33CK32MC105-E/M4
✅ Drop-In ⚠️ Specs Unverified✓ In Stock
$3.2 / Unit
View Datasheet →DSPIC33CK64MP105-I/M4 Maximum Ratings & Electrical Characteristics
| Core | 16-bit dsPIC DSC |
| Maximum CPU Speed | 100 MHz |
| Flash Program Memory | 64 KB (64K x 8) |
| SRAM | 8 KB |
| Supply Voltage | 3.3 V |
| Number of I/Os | 39 |
| ADC Resolution | 12-bit |
| Integrated Op Amps | Yes |
| PWM | MCCP/SCCP configurable PWM (up to 6 outputs per MCCP) |
| Serial Interfaces | I2C, I2S, SPI, UART |
| DMA Channels | 4 |
| Package / Case | 48-UQFN Exposed Pad (M4) |
| Mounting Type | Surface Mount |
| Operating Temperature | -40C to +85C (TA) |
| MSL Level | 1 (Unlimited) |
| Series | dsPIC 33CK |
| Product Status | Active |
| Packaging | Tube |
DSPIC33CK64MP105-I/M4 48-uqfn exposed pad (m4) Pin Configuration Guide
Pin configuration for DSPIC33CK64MP105-I/M4 (48-uqfn exposed pad (m4) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for DSPIC33CK64MP105-I/M4.
Refer to the datasheet for full pin configuration.
Typical Applications
DSPIC33CK64MP105-I/M4 is suitable for 6 applications: Digital Power Supplies, Brushless DC / PMSM Motor Control, Advanced Sensing Systems, Co-Processor / Host-Assist Control, Industrial Automation and PFC Front Ends, Audio and Communication Signal Processing.
Digital Power Supplies
The DSPIC33CK64MP105-I/M4 is purpose-built for digitally controlled power converters such as LLC resonant stages, totem-pole PFC and synchronous buck supplies. Its 100 MHz core executes compensator mathematics fast enough for control loops at hundreds of kHz switching frequency, while the high-resolution PWM from MCCP modules provides fine duty-cycle adjustment critical for high-frequency regulation accuracy. The integrated op amps amplify current-shunt signals and the 12-bit ADC samples them with 4 DMA channels moving results to RAM without CPU overhead. Placed as the sole controller between the feedback divider and gate drivers, it eliminates analog error amplifiers but adds firmware validation effort compared to a hardware controller.
Recommended
Brushless DC / PMSM Motor Control
Field Oriented Control (FOC) of PMSM and BLDC motors is a primary target for the dsPIC33CK64MP105 family. The 100 MHz core with DSP MAC instructions computes Clarke/Park transforms and PI current loops within a single PWM period even at 20-50 kHz switching. MCCP modules generate center-aligned complementary PWM with programmable dead-time, while the on-chip op amps condition low-side shunt currents directly into the 12-bit ADC. Using this DSC removes the external op-amp stage required with MC-series parts, cutting BOM cost in 48-pin designs. Trade-off: firmware-based control requires careful ISR budgeting versus a dedicated motor-control ASIC.
Recommended
Advanced Sensing Systems
The DSPIC33CK64MP105-I/M4 suits multi-channel sensing front-ends where analog conditioning and digital processing must coexist on one chip. Three integrated op amps can be configured as gain stages for bridge or shunt sensors, feeding the 12-bit ADC with results streamed by DMA. The 100 MHz DSP engine runs filtering, RMS computation or FFT-based analysis on-node, and UART/SPI/I2C/I2S interfaces export processed data. Compared to discrete op-amp plus generic MCU designs, it shortens the analog path and improves noise immunity. Design consideration: budget the op-amp bandwidth versus sensor signal frequency per the manufacturer datasheet electrical specifications.
Recommended
Co-Processor / Host-Assist Control
The dsPIC33CK64MP105 works effectively as a dedicated control co-processor beside a host MCU or SoC, offloading hard real-time loops. The 100 MHz core handles deterministic tasks (PWM generation, ADC-based current loops) while communicating status and setpoints over UART, SPI or I2C to the host. The 8 KB RAM and 64 KB Flash accommodate fixed-point control firmware with margin. In this role the M4's 48-pin UQFN footprint keeps board area small, and multiple PGECx/PGEDx pairs simplify in-circuit programming even when the host owns the main bus. Benefit: isolates real-time firmware release cycles from host software updates.
Recommended
Industrial Automation and PFC Front Ends
Industrial equipment requiring precise power-factor correction, inverter stages, or embedded motion benefits from the DSPIC33CK64MP105-I/M4's combination of a 100 MHz DSC core, high-resolution PWM and industrial -40C to +85C operation. In an AC-drive front end, the ADC with DMA samples bus voltage and phase currents while MCCP PWM modules drive the inverter bridge; the DSP engine executes harmonic compensation in firmware. Its Flash self-programming enables field firmware updates through UART bootloaders, valuable in installed equipment. Compared to analog PFC controllers, it adds configurability and telemetry at the cost of firmware development effort.
Recommended
Audio and Communication Signal Processing
With a DSP-enhanced 16-bit core, barrel shifter, MAC instructions and an I2S serial interface, the DSPIC33CK64MP105-I/M4 can implement digital audio filtering, sample-rate conversion or modem-type processing in cost-sensitive products. The I2S port connects directly to audio codecs, while 4 DMA channels sustain continuous stream throughput to the 8 KB SRAM ring buffers. The 100 MIPS budget supports several cascaded biquad filters at standard audio sample rates. Trade-off: for high-fidelity floating-point processing, a 32-bit FPU-equipped MCU is preferable; this DSC excels where fixed-point processing and rich control peripherals must coexist.
Recommended
Recommended Products Summary
Engineering reference data for DSPIC33CK64MP105-I/M4 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | DSPIC33CK64MP105-H/M4 | DSPIC33CK64MC105T-I/M4 | DSPIC33CK32MC105-E/M4 |
|---|---|---|---|---|
| Package | 48-UQFN (M4) | 48-UQFN (M4) - same | 48-UQFN (M4) - same | 48-UQFN (M4) - same |
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Core Speed | 100 MHz | 64 MHz | 100 MHz | 100 MHz |
| Flash Memory | 64 KB | 64 KB | 64 KB | 32 KB |
| SRAM | 8 KB | 8 KB | 8 KB | 8 KB |
| Integrated Op Amps | Yes (MP variant) | Yes (same die) | No (MC variant) | No (MC variant) |
| Serial Interfaces | I2C, I2S, SPI, UART | I2C, I2S, SPI, UART | I2C, SPI, UART | I2C, SPI, UART |
Key Differentiators
- Integrated op amps for current sensing (vs DSPIC33CK64MC105T-I/M4)
- 100 MHz maximum core speed (vs DSPIC33CK64MP105-H/M4)
- Large 64 KB Flash for control plus bootloader (vs DSPIC33CK32MC105-E/M4)
Design Notes
The 48-UQFN (M4) exposed-pad package requires the center thermal pad to be soldered to a grounded PCB array of vias. Because this is the primary ground return for the DSC core and analog peripherals, an incomplete reflow of the exposed pad causes intermittent resets and ADC noise that are difficult to diagnose. Use an X2 or windowed solder-mask pattern on the pad array, and inspect with X-ray for volume production. Follow the Microchip family datasheet (DS70005363E) land-pattern dimensions exactly.
The dsPIC33CK core is fed from an internal regulator whose external VCAP capacitor is mandatory for stable operation. Place the VCAP capacitor as close to its pin as possible with a low-impedance ground return, and never draw external load current from it. Decouple each VDD pin with 100 nF ceramics plus one bulk capacitor per rail. Estimated: at 3.3 V and typical active currents for the 100 MHz core, supply decoupling sized per the datasheet electrical characteristics is sufficient; verify brown-out thresholds are enabled for reliability in industrial environments.
The device has multiple PGECx/PGEDx programming pairs: any pair works, but ICSPCLK and ICSPDAT must come from the SAME pair (e.g., PGEC2 with PGED2), and dedicated PGD/PGC pins should not be loaded with pull-downs or LEDs that interfere with programming. All VDD and VSS pins must be connected even if the design appears to function with one floating. Per the Microchip Flash Programming Specification (70005352), MCLR must be pulled up (10k) with a diode clamp arrangement for ICSP high-voltage entry.
Compliance Information
Compliance status not stated in the provided verified web data; confirm RoHS/REACH status on the Microchip product page or distributor compliance certificates before export-controlled production use.
