EPM3128ATC144-10 - 128-Macro MAX 3000A CPLD | Altera | TQFP-144
MPN: EPM3128ATC144-10 β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $11.84 | $11.84 |
| 10 | $10.65 | $106.50 |
| 100 | $8.95 | $895.00 |
| 500 | $7.45 | $3,725.00 |
| 1,000 | $6.2 | $6,200.00 |
Drop-in alternatives for EPM3128ATC144-10 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM3128ATC144-10N
β Drop-Inβ In Stock
$6.56 / Unit
View Datasheet βEPM3128ATC144-7N
β Drop-Inβ In Stock
$9.25 / Unit
View Datasheet βEPM3128ATC144-7
β Drop-Inβ In Stock
$8.1 / Unit
View Datasheet βEPM3128ATC100-10
β Drop-Inβ In Stock
$8.1 / Unit
View Datasheet βEPM3128ATC100-10N
β Drop-Inβ In Stock
$5.2 / Unit
View Datasheet βEPM3128ATC144-10 Maximum Ratings & Electrical Characteristics
| Family | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 128 |
| User I/Os | 96 |
| Usable Gates | 2,500 (typical) |
| Logic Elements / LABs | 4 Logic Array Blocks |
| Propagation Delay (tPD) | 10 ns (speed grade -10) |
| Counter Frequency (fCNT) | Up to 227.3 MHz |
| Supply Voltage (VCCINT) | 3.3 V |
| MultiVolt I/O Interface | 1.5V / 1.8V / 2.5V / 3.3V |
| In-System Programmability | IEEE Std. 1532 compliant |
| Boundary-Scan Test | IEEE Std. 1149.1 (JTAG) |
| Configuration Memory | EEPROM (non-volatile, instant-on) |
| Package | 144-pin TQFP (TQ144) |
| Mounting Type | Surface Mount |
| Operating Temperature | 0C to +70C (commercial) |
| RoHS Status | Compliant |
| Lead-Free | Yes |
EPM3128ATC144-10 Pin Configuration
| Pin 1 | OE1/GCLK2 β Global output enable or secondary global clock input |
| Pin 2 | I/O β User I/O pin |
| Pin 3 | I/O β User I/O pin |
| Pin 4 | I/O β User I/O pin |
| Pin 5 | I/O β User I/O pin |
| Pin 6 | I/O β User I/O pin |
| Pin 7 | I/O β User I/O pin |
| Pin 8 | VCCIO β I/O supply voltage |
| Pin 9 | I/O β User I/O pin |
| Pin 10 | I/O β User I/O pin |
| Pin 11 | I/O β User I/O pin |
| Pin 12 | GND β Ground |
| Pin 13 | I/O β User I/O pin |
| Pin 14 | I/O β User I/O pin |
| Pin 15 | I/O β User I/O pin |
| Pin 16 | I/O β User I/O pin |
| Pin 17 | I/O β User I/O pin |
| Pin 18 | I/O β User I/O pin |
| Pin 19 | I/O β User I/O pin |
| Pin 20 | I/O β User I/O pin |
| Pin 21 | GND β Ground |
| Pin 22 | I/O β User I/O pin |
| Pin 23 | I/O β User I/O pin |
| Pin 24 | I/O β User I/O pin |
| Pin 25 | I/O β User I/O pin |
| Pin 26 | I/O β User I/O pin |
| Pin 27 | I/O β User I/O pin |
| Pin 28 | I/O β User I/O pin |
| Pin 29 | I/O β User I/O pin |
| Pin 30 | I/O β User I/O pin |
| Pin 31 | TDI β JTAG Test Data In (IEEE 1149.1) |
| Pin 32 | VCCIO β I/O supply voltage |
| Pin 33 | TDO β JTAG Test Data Out (IEEE 1149.1) |
| Pin 34 | I/O β User I/O pin |
| Pin 35 | TMS β JTAG Test Mode Select (IEEE 1149.1) |
| Pin 36 | I/O β User I/O pin |
| Pin 37 | TCK β JTAG Test Clock (IEEE 1149.1) |
| Pin 38 | GND β Ground |
| Pin 39 | I/O β User I/O pin |
| Pin 40 | I/O β User I/O pin |
| Pin 41 | I/O β User I/O pin |
| Pin 42 | I/O β User I/O pin |
| Pin 43 | GCLK1 β Global clock input 1 |
| Pin 44 | OE2/GCLK3 β Global output enable or global clock 3 |
| Pin 45 | I/O β User I/O pin |
| Pin 46 | I/O β User I/O pin |
| Pin 47 | I/O β User I/O pin |
| Pin 48 | I/O β User I/O pin |
| Pin 49 | GND β Ground |
| Pin 50 | I/O β User I/O pin |
| Pin 51 | I/O β User I/O pin |
| Pin 52 | I/O β User I/O pin |
| Pin 53 | I/O β User I/O pin |
| Pin 54 | I/O β User I/O pin |
| Pin 55 | I/O β User I/O pin |
| Pin 56 | I/O β User I/O pin |
| Pin 57 | VCCIO β I/O supply voltage |
| Pin 58 | I/O β User I/O pin |
| Pin 59 | I/O β User I/O pin |
| Pin 60 | I/O β User I/O pin |
| Pin 61 | I/O β User I/O pin |
| Pin 62 | I/O β User I/O pin |
| Pin 63 | I/O β User I/O pin |
| Pin 64 | I/O β User I/O pin |
| Pin 65 | I/O β User I/O pin |
| Pin 66 | GND β Ground |
| Pin 67 | I/O β User I/O pin |
| Pin 68 | I/O β User I/O pin |
| Pin 69 | I/O β User I/O pin |
| Pin 70 | I/O β User I/O pin |
| Pin 71 | I/O β User I/O pin |
| Pin 72 | I/O β User I/O pin |
| Pin 73 | I/O β User I/O pin |
| Pin 74 | I/O β User I/O pin |
| Pin 75 | I/O β User I/O pin |
| Pin 76 | I/O β User I/O pin |
| Pin 77 | GND β Ground |
| Pin 78 | I/O β User I/O pin |
| Pin 79 | I/O β User I/O pin |
| Pin 80 | I/O β User I/O pin |
| Pin 81 | I/O β User I/O pin |
| Pin 82 | I/O β User I/O pin |
| Pin 83 | I/O β User I/O pin |
| Pin 84 | I/O β User I/O pin |
| Pin 85 | I/O β User I/O pin |
| Pin 86 | I/O β User I/O pin |
| Pin 87 | GND β Ground |
| Pin 88 | I/O β User I/O pin |
| Pin 89 | I/O β User I/O pin |
| Pin 90 | I/O β User I/O pin |
| Pin 91 | I/O β User I/O pin |
| Pin 92 | I/O β User I/O pin |
| Pin 93 | I/O β User I/O pin |
| Pin 94 | I/O β User I/O pin |
| Pin 95 | VCCIO β I/O supply voltage |
| Pin 96 | I/O β User I/O pin |
| Pin 97 | I/O β User I/O pin |
| Pin 98 | I/O β User I/O pin |
| Pin 99 | I/O β User I/O pin |
| Pin 100 | GND β Ground |
| Pin 101 | I/O β User I/O pin |
| Pin 102 | I/O β User I/O pin |
| Pin 103 | I/O β User I/O pin |
| Pin 104 | I/O β User I/O pin |
| Pin 105 | I/O β User I/O pin |
| Pin 106 | I/O β User I/O pin |
| Pin 107 | I/O β User I/O pin |
| Pin 108 | I/O β User I/O pin |
| Pin 109 | I/O β User I/O pin |
| Pin 110 | VCCINT β Core supply voltage (3.3V) |
| Pin 111 | I/O β User I/O pin |
| Pin 112 | I/O β User I/O pin |
| Pin 113 | I/O β User I/O pin |
| Pin 114 | I/O β User I/O pin |
| Pin 115 | I/O β User I/O pin |
| Pin 116 | I/O β User I/O pin |
| Pin 117 | I/O β User I/O pin |
| Pin 118 | GND β Ground |
| Pin 119 | I/O β User I/O pin |
| Pin 120 | I/O β User I/O pin |
| Pin 121 | I/O β User I/O pin |
| Pin 122 | I/O β User I/O pin |
| Pin 123 | I/O β User I/O pin |
| Pin 124 | I/O β User I/O pin |
| Pin 125 | I/O β User I/O pin |
| Pin 126 | I/O β User I/O pin |
| Pin 127 | I/O β User I/O pin |
| Pin 128 | GND β Ground |
| Pin 129 | I/O β User I/O pin |
| Pin 130 | I/O β User I/O pin |
| Pin 131 | I/O β User I/O pin |
| Pin 132 | I/O β User I/O pin |
| Pin 133 | I/O β User I/O pin |
| Pin 134 | I/O β User I/O pin |
| Pin 135 | VCCIO β I/O supply voltage |
| Pin 136 | I/O β User I/O pin |
| Pin 137 | I/O β User I/O pin |
| Pin 138 | I/O β User I/O pin |
| Pin 139 | I/O β User I/O pin |
| Pin 140 | I/O β User I/O pin |
| Pin 141 | I/O β User I/O pin |
| Pin 142 | I/O β User I/O pin |
| Pin 143 | I/O β User I/O pin |
| Pin 144 | I/O β User I/O pin |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM3128ATC144-10 is suitable for 6 applications: Microcontroller I/O Expansion and Bus Decoding, Industrial Control and Factory Automation, Legacy Telecom and Networking Equipment, Display Interface and Video Timing Controller, Power Supply Sequencing and Hot-Swap Control, Automotive Infotainment and Body Electronics.
Microcontroller I/O Expansion and Bus Decoding
The EPM3128ATC144-10's 96 user I/Os and 128 macro cells make it an ideal I/O expander for 8-bit and 16-bit microcontrollers that lack sufficient pins. With a deterministic 10 ns propagation delay and 3.3V core with multi-voltage I/O, it can decode 24-bit address buses, generate chip-select signals for memory banks, and arbitrate multiple peripheral requests in real time. The EEPROM-based instant-on configuration eliminates firmware boot latency - critical in industrial controllers that must respond within microseconds of power-up. Use it for address decoding, peripheral chip-select generation, and glue-logic between the MCU and external devices such as SRAM, Flash, ADCs, or UARTs. The 4-LAB architecture comfortably accommodates 8-to-16 address line decoders while leaving headroom for status LEDs and interrupt steering.
Recommended
Industrial Control and Factory Automation
In industrial PLCs, motor controllers, and factory automation systems, the EPM3128ATC144-10 serves as the deterministic glue logic between sensors, optocouplers, and the central processor. Its 10 ns tPD ensures sub-microsecond response to safety interrupts - critical for E-stop circuits and overcurrent shutdown where 1 ms of latency can cause equipment damage. The commercial 0C-to-70C operating range suits factory floor environments, while the JTAG (IEEE 1149.1) boundary-scan test interface simplifies in-circuit test on densely populated control boards. The 96 I/Os easily handle 32 digital inputs, 16 relay-driver outputs, 4 quadrature-decoder channels for encoder feedback, and an RS-485 transceiver interface - all within a single device. Multi-voltage I/O bank support allows direct interface to 5V sensors and 3.3V logic in mixed-voltage systems without level shifters.
Recommended
Legacy Telecom and Networking Equipment
Telecom backplane systems, T1/E1 line cards, and legacy router line-interface modules continue to deploy the EPM3128ATC144-10 for HDLC framing, time-slot assignment, and bus-isolation functions. With counter frequencies up to 227.3 MHz, the device can implement UART baud-rate generators, HDLC bit-stuffers, and 8B/10B line-code state machines at standard telecom bit rates. The instant-on non-volatile EEPROM configuration prevents the line card from transmitting garbage frames during FPGA-based host-processor firmware load - a critical reliability advantage. The 144-pin TQFP package provides the I/O count needed for 8-bit parallel PCM highway interfaces, while the multi-voltage I/O banks interface directly to 1.8V FPGAs and 3.3V PHY devices. Designers value its -40C-to-85C industrial temperature variants for outdoor cabinet deployments.
Recommended
Display Interface and Video Timing Controller
The EPM3128ATC144-10 is widely used in LCD/LED display controller boards, video projectors, and digital signage systems where it generates pixel clocks, horizontal/vertical sync, and blanking signals. Its 227.3 MHz counter speed easily handles SVGA (800x600 at 60 Hz, 40 MHz pixel clock) and XGA (1024x768 at 60 Hz, 65 MHz pixel clock) timing requirements. The 10 ns propagation delay gives designers generous margin for sync-pulse generation and inter-channel skew control. With 96 I/Os, the device can drive 24-bit parallel RGB interfaces plus separate HSYNC, VSYNC, DE, and clock signals while also handling backlight PWM dimming and OSD pixel overlay. The deterministic timing eliminates the need for software calibration - a major advantage over MCU-based timing generation.
Recommended
Power Supply Sequencing and Hot-Swap Control
Multi-rail systems (FPGA + DDR memory + ASIC + transceivers) require precisely ordered power-up and power-down to prevent latch-up and in-rush damage. The EPM3128ATC144-10 implements this sequencing with 96 I/Os that can monitor PG (power-good) signals from 8-to-12 regulators and sequence their enable pins in user-defined order with millisecond-resolution delays. Its EEPROM-based instant-on configuration ensures the sequencing logic is active before any of the rails are stable - unlike an MCU-based sequencer that needs firmware boot time. The deterministic 10 ns propagation delay allows glitch-free hot-swap insertion detection with sub-microsecond response. Designers can also implement fault logging, retry logic, and I2C/PMBus status reporting on spare I/Os.
Recommended
Automotive Infotainment and Body Electronics
Body control modules, instrument clusters, and infotainment head units in legacy automotive platforms use the EPM3128ATC144-10 for CAN/LIN bus bridging, headlight matrix control, and stepper-motor driving for HVAC dampers. With 96 user I/Os, it can manage 8-to-12 LIN slaves, decode CAN-FD message IDs, and drive stepper motor H-bridges simultaneously. The MAX 3000A architecture's deterministic 10 ns timing is critical for CAN bus arbitration - jitter from soft-core logic could cause bit-stuffing errors. Designers appreciate the JTAG boundary-scan interface for in-circuit test on densely populated automotive PCBs, where probe access is limited. Note: for AEC-Q100 qualified automotive applications, the EPM3128ATC144-10N industrial-grade variant is preferred.
Recommended
Recommended Products Summary
Engineering reference data for EPM3128ATC144-10 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM3128ATC144-10N | EPM3128ATC144-7N | EPM3128ATC144-7 | EPM3128ATC100-10 | EPM3128ATC100-10N |
|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | TQFP-144 | TQFP-144 - same | TQFP-144 - same | TQFP-144 - same | TQFP-100 - smaller | TQFP-100 - smaller |
| Macro Cells | 128 | 128 | 128 | 128 | 128 | 128 |
| User I/Os | 96 | 96 | 96 | 96 | 80 | 80 |
| Propagation Delay (tPD) | 10 ns | 10 ns | 7.5 ns (faster) | 7.5 ns (faster) | 10 ns | 10 ns |
| Counter Frequency (fCNT) | 227.3 MHz | 227.3 MHz | [DATA_NEEDED] | [DATA_NEEDED] | 227.3 MHz | 227.3 MHz |
| Core Voltage (VCCINT) | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| RoHS / Lead-Free | RoHS / Lead-Free | RoHS / Lead-Free (N-suffix) | RoHS / Lead-Free (N-suffix) | Leaded finish | Leaded finish | RoHS / Lead-Free (N-suffix) |
| Programming Compatibility | IEEE 1532 ISP, JTAG | Bitstream-compatible | Bitstream-compatible (same family) | Bitstream-compatible (same family) | Bitstream-compatible (smaller pinout) | Bitstream-compatible (smaller pinout) |
Key Differentiators
- Drop-in RoHS-compliant variant exists for new designs (vs EPM3128ATC144-10N)
- Faster speed grade available in same package (vs EPM3128ATC144-7N)
- Smaller-package variant for cost-down designs (vs EPM3128ATC100-10N)
Design Notes
Estimated: at 3.3V VCCINT and 96 I/Os each switching at 10 MHz with 30 pF external load, the EPM3128ATC144-10's dynamic current consumption can reach approximately 80-120 mA. Place at least four 0.1 uF X7R ceramic decoupling capacitors within 5 mm of the VCCINT and VCCIO pins (one per quadrant of the TQFP-144 package). Add a single 10 uF tantalum or ceramic bulk capacitor near the package to handle simultaneous switching transients on multiple I/O banks. The I/O supply voltage (VCCIO) determines the output logic high level - for 3.3V LVCMOS output to 1.8V LVCMOS inputs, use a 1.8V VCCIO bank with internal level-shifting enabled in the Quartus II pin planner.
Route the JTAG signals (TDI, TDO, TMS, TCK) in a star topology from the JTAG connector to the CPLD, with TCK having a series 33 ohm damping resistor within 25 mm of the device to prevent ringing on the rising edge of the 10 MHz (or higher) test clock. Avoid routing JTAG signals parallel to fast-switching I/O traces for more than 25 mm to prevent crosstalk into the JTAG state machine. The TQFP-144 has a 0.5 mm pitch - ensure your PCB fabrication capability supports 0.4 mm via-to-trace clearance and 0.15 mm trace width for escape routing from inner rows.
A common mistake is to assume the EPM3128ATC144-10 is drop-in compatible with the EPM7128AETC144-10N from the MAX 7000A family. Although both share the 144-pin TQFP package, they have different JTAG IDs, different programming files, different macro cell architectures, and different VCC requirements - they are NOT bitstream-compatible. Always recompile your Quartus II project with the correct device family selected before programming. Another pitfall is mixing up the -10 and -10N suffixes: both are functional equivalents but only the -10N has RoHS-compliant lead-free terminal finish - choose the -10N for new designs requiring Pb-free assembly.
For designs with multiple high-speed clock outputs (e.g., DDR memory interfaces), use the dedicated GCLK1 input (pin 43) as the primary clock source and route it with a 50 ohm microstrip trace and 33 ohm source-termination resistor. Assign clock outputs to the same I/O bank to minimize bank-to-bank skew. For designs using the JTAG boundary-scan for in-circuit test, ensure the TRST pin (if present in your variant) is tied high through a 10 kohm resistor to VCCIO to keep the JTAG TAP controller in known state during power-up; do not leave TRST floating.
Compliance Information
RoHS compliant per Altera product page. The 'N' suffix denotes lead-free finish - choose EPM3128ATC144-10N for explicit RoHS compliance. AEC-Q100 qualification is NOT available - for automotive applications requiring it, migrate to EPM240T100C5N (MAX II family) with additional qualification testing.
