EPM3128ATI144-10 - MAX 3000A CPLD 128 Macro 98 I/O TQFP-144 | Intel/Altera
MPN: EPM3128ATI144-10 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $14.05 | $1,405.00 |
| 500 | $12.4 | $6,200.00 |
| 1,000 | $10.85 | $10,850.00 |
Drop-in alternatives for EPM3128ATI144-10 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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EPM3128ATC144-10N
✅ Drop-In✓ In Stock
$6.56 / Unit
View Datasheet →EPM3128ATC144-10
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$6.2 / Unit
View Datasheet →EPM3128ATC144-7N
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$9.25 / Unit
View Datasheet →EPM3128ATC144-5N
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$13.75 / Unit
View Datasheet →EPM3128ATC144-7
✅ Drop-In✓ In Stock
$8.1 / Unit
View Datasheet →EPM3128ATI144-10 Maximum Ratings & Electrical Characteristics
| Family | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Usable Gates | 2,500 |
| Macro Cells | 128 |
| Logic Array Blocks (LABs) | 8 |
| User I/Os | 98 |
| Pin Count | 144 |
| Package | TQFP-144 (FINE LINE) |
| Supply Voltage (VCCINT) | 3.3 V |
| Pin-to-Pin Delay | 10 ns (speed grade -10) |
| Counter Frequency | 98 MHz typical |
| Logic Family | CMOS, EEPROM-based |
| Programming Interface | IEEE 1149.1 JTAG (ISP) |
| PCI Compliance | PCI Local Bus Spec Rev 2.2 (speed grades -4 to -10) |
| Operating Temperature | -40C to +85C (Industrial) |
| Mounting Type | Surface Mount (Gull-Wing TQFP) |
| RoHS Status | Compliant (lead-free TQFP) |
EPM3128ATI144-10 Pin Configuration
| Pin 1 | I/O — User I/O pin (per datasheet pin table) |
| Pin 2 | I/O — User I/O pin |
| Pin 3 | I/O — User I/O pin |
| Pin 4 | I/O — User I/O pin |
| Pin 5 | I/O — User I/O pin |
| Pin 6 | I/O — User I/O pin |
| Pin 7 | I/O — User I/O pin |
| Pin 8 | I/O — User I/O pin |
| Pin 9 | I/O — User I/O pin |
| Pin 10 | I/O — User I/O pin |
| Pin 11 | I/O — User I/O pin |
| Pin 12 | I/O — User I/O pin |
| Pin 13 | GND — Ground |
| Pin 14 | I/O — User I/O pin |
| Pin 15 | I/O — User I/O pin |
| Pin 16 | I/O — User I/O pin |
| Pin 17 | I/O — User I/O pin |
| Pin 18 | I/O — User I/O pin |
| Pin 19 | I/O — User I/O pin |
| Pin 20 | I/O — User I/O pin |
| Pin 21 | I/O — User I/O pin |
| Pin 22 | I/O — User I/O pin |
| Pin 23 | I/O — User I/O pin |
| Pin 24 | I/O — User I/O pin |
| Pin 25 | I/O — User I/O pin |
| Pin 26 | I/O — User I/O pin |
| Pin 27 | GND — Ground |
| Pin 28 | I/O — User I/O pin |
| Pin 29 | I/O — User I/O pin |
| Pin 30 | I/O — User I/O pin |
| Pin 31 | I/O — User I/O pin |
| Pin 32 | I/O — User I/O pin |
| Pin 33 | I/O — User I/O pin |
| Pin 34 | I/O — User I/O pin |
| Pin 35 | I/O — User I/O pin |
| Pin 36 | I/O — User I/O pin |
| Pin 37 | I/O — User I/O pin |
| Pin 38 | I/O — User I/O pin |
| Pin 39 | I/O — User I/O pin |
| Pin 40 | I/O — User I/O pin |
| Pin 41 | GND — Ground |
| Pin 42 | I/O — User I/O pin |
| Pin 43 | I/O — User I/O pin |
| Pin 44 | I/O — User I/O pin |
| Pin 45 | I/O — User I/O pin |
| Pin 46 | I/O — User I/O pin |
| Pin 47 | I/O — User I/O pin |
| Pin 48 | I/O — User I/O pin |
| Pin 49 | I/O — User I/O pin |
| Pin 50 | I/O — User I/O pin |
| Pin 51 | I/O — User I/O pin |
| Pin 52 | I/O — User I/O pin |
| Pin 53 | I/O — User I/O pin |
| Pin 54 | I/O — User I/O pin |
| Pin 55 | GND — Ground |
| Pin 56 | I/O — User I/O pin |
| Pin 57 | I/O — User I/O pin |
| Pin 58 | I/O — User I/O pin |
| Pin 59 | I/O — User I/O pin |
| Pin 60 | I/O — User I/O pin |
| Pin 61 | I/O — User I/O pin |
| Pin 62 | I/O — User I/O pin |
| Pin 63 | I/O — User I/O pin |
| Pin 64 | I/O — User I/O pin |
| Pin 65 | I/O — User I/O pin |
| Pin 66 | I/O — User I/O pin |
| Pin 67 | I/O — User I/O pin |
| Pin 68 | I/O — User I/O pin |
| Pin 69 | GND — Ground |
| Pin 70 | I/O — User I/O pin |
| Pin 71 | I/O — User I/O pin |
| Pin 72 | I/O — User I/O pin |
| Pin 73 | I/O — User I/O pin |
| Pin 74 | I/O — User I/O pin |
| Pin 75 | I/O — User I/O pin |
| Pin 76 | I/O — User I/O pin |
| Pin 77 | I/O — User I/O pin |
| Pin 78 | I/O — User I/O pin |
| Pin 79 | I/O — User I/O pin |
| Pin 80 | I/O — User I/O pin |
| Pin 81 | I/O — User I/O pin |
| Pin 82 | I/O — User I/O pin |
| Pin 83 | GND — Ground |
| Pin 84 | I/O — User I/O pin |
| Pin 85 | I/O — User I/O pin |
| Pin 86 | I/O — User I/O pin |
| Pin 87 | I/O — User I/O pin |
| Pin 88 | I/O — User I/O pin |
| Pin 89 | I/O — User I/O pin |
| Pin 90 | I/O — User I/O pin |
| Pin 91 | I/O — User I/O pin |
| Pin 92 | I/O — User I/O pin |
| Pin 93 | I/O — User I/O pin |
| Pin 94 | I/O — User I/O pin |
| Pin 95 | I/O — User I/O pin |
| Pin 96 | I/O — User I/O pin |
| Pin 97 | GND — Ground |
| Pin 98 | TDI — JTAG Test Data In |
| Pin 99 | TMS — JTAG Test Mode Select |
| Pin 100 | TCK — JTAG Test Clock |
| Pin 101 | I/O — User I/O pin |
| Pin 102 | I/O — User I/O pin |
| Pin 103 | I/O — User I/O pin |
| Pin 104 | I/O — User I/O pin |
| Pin 105 | I/O — User I/O pin |
| Pin 106 | I/O — User I/O pin |
| Pin 107 | I/O — User I/O pin |
| Pin 108 | I/O — User I/O pin |
| Pin 109 | I/O — User I/O pin |
| Pin 110 | I/O — User I/O pin |
| Pin 111 | GND — Ground |
| Pin 112 | I/O — User I/O pin |
| Pin 113 | I/O — User I/O pin |
| Pin 114 | I/O — User I/O pin |
| Pin 115 | I/O — User I/O pin |
| Pin 116 | I/O — User I/O pin |
| Pin 117 | I/O — User I/O pin |
| Pin 118 | I/O — User I/O pin |
| Pin 119 | I/O — User I/O pin |
| Pin 120 | I/O — User I/O pin |
| Pin 121 | I/O — User I/O pin |
| Pin 122 | I/O — User I/O pin |
| Pin 123 | I/O — User I/O pin |
| Pin 124 | I/O — User I/O pin |
| Pin 125 | GND — Ground |
| Pin 126 | I/O — User I/O pin |
| Pin 127 | I/O — User I/O pin |
| Pin 128 | I/O — User I/O pin |
| Pin 129 | I/O — User I/O pin |
| Pin 130 | I/O — User I/O pin |
| Pin 131 | I/O — User I/O pin |
| Pin 132 | I/O — User I/O pin |
| Pin 133 | I/O — User I/O pin |
| Pin 134 | I/O — User I/O pin |
| Pin 135 | I/O — User I/O pin |
| Pin 136 | I/O — User I/O pin |
| Pin 137 | I/O — User I/O pin |
| Pin 138 | I/O — User I/O pin |
| Pin 139 | GND — Ground |
| Pin 140 | TDO — JTAG Test Data Out |
| Pin 141 | I/O — User I/O pin |
| Pin 142 | I/O — User I/O pin |
| Pin 143 | I/O — User I/O pin |
| Pin 144 | I/O — User I/O pin |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM3128ATI144-10 is suitable for 7 applications: Industrial Control Glue Logic, PCI Bus Address Decoding, Multi-Rail Power Sequencing Controller, Microcontroller Bus Interface Bridging, Peripheral Expansion Logic (GPIO Extender), Legacy Peripheral Replacement / State Machine, Automotive Body Electronics.
Industrial Control Glue Logic
The EPM3128ATI144-10's 128 macro cells and deterministic 10 ns pin-to-pin delay make it ideal for industrial glue-logic between microcontrollers, sensors, and actuators in factory automation. The device replaces 5-10 discrete 74-series logic ICs with a single non-volatile part, freeing PCB space and reducing BOM cost. Its industrial -40C to +85C temperature range tolerates cabinet-mounted environments and -25C cold-start conditions. Use it for address decoding, I/O expansion, watchdog timing, and interrupt prioritization in PLC backplanes. The JTAG ISP allows field re-programming via the controller's existing test header, eliminating the need for socketed PROMs and reducing service downtime. Estimated: power consumption is roughly 100-150 mW at 3.3 V with all I/O toggling, so a small LDO is sufficient.
Recommended
PCI Bus Address Decoding
In PCI 2.2 add-in cards the EPM3128ATI144-10 provides PCI-compliant chip-select generation and bus-cycle decoding for memory and I/O windows. The 3.3-V core with 5-V-tolerant I/O directly interfaces to PCI bus signals, and the -10 speed grade (10 ns pin-to-pin) comfortably meets the 33 MHz PCI clock period with timing margin. With 98 user I/Os the device can decode up to 4-6 address ranges plus generate the active-low FRAME, IRDY, and TRDY enable signals for downstream peripherals. The JTAG interface allows post-assembly programming of the device's EEPROM image directly on the PCI card, simplifying board bring-up. Designers should reserve the four JTAG pins (TCK/TMS/TDI/TDO) and route them to a 4-pin header for boundary-scan test access.
Recommended
Multi-Rail Power Sequencing Controller
The EPM3128ATI144-10's instant-on EEPROM-based logic makes it a reliable power-sequencing controller for systems with strict rail-order requirements (e.g., FPGA core before I/O before transceivers). With 98 user I/Os the device can monitor up to 12-15 PG (power-good) inputs and assert 12-15 EN lines to downstream regulators with programmable delays implemented as on-chip counters. The 10 ns pin-to-pin delay gives sub-microsecond sequencing resolution. Industrial temperature rating ensures cold-boot reliability in outdoor and automotive systems. Use the JTAG port to reprogram sequence tables during development without replacing the part. Estimated: each rail-enable line can source/sink 25 mA; for higher current, buffer with a discrete MOSFET driver.
Recommended
Microcontroller Bus Interface Bridging
The EPM3128ATI144-10 bridges mismatched buses between a 16-bit microcontroller, an SRAM bank, an LCD controller, and an external peripheral. Its 98 user I/Os handle multiple chip-selects, RD/WR strobes, and address-latch enable signals simultaneously, while the deterministic 10 ns timing matches legacy 8051, PIC, and ARM7 external-bus timing without wait-state insertion. The EEPROM configuration retains the bus map across power cycles, eliminating boot-up glitching. Industrial temperature grade supports outdoor HMI panels. Designers should place the device close to the microcontroller to minimize propagation skew and use the JTAG port to revise address maps in the field.
Recommended
Peripheral Expansion Logic (GPIO Extender)
When a microcontroller runs out of GPIO pins, the EPM3128ATI144-10 adds 98 configurable I/Os with interrupt and timer functions, accessible over a 3-wire SPI or I2C-like interface from the host. Each CPLD I/O can be individually set as input, output, or open-drain with internal pull-up. The instant-on EEPROM image lets I/O defaults be safe at power-up without firmware intervention, critical for fail-safe system designs. The 10 ns propagation delay enables debounced contact-input scanning at mechanical-switch rates (>1 kHz). Industrial temperature rating suits appliance and HVAC controllers.
Recommended
Legacy Peripheral Replacement / State Machine
The EPM3128ATI144-10 replaces obsolete TTL/CMOS state-machine ICs (e.g., 74LS194 shift-register chains, custom PAL/GAL sequencers) with a single reprogrammable device. A 144-pin TQFP occupies the same board area as 3-4 SOIC-16 PLD packages and offers far higher functional density. The 128 macro cells can encode multi-state FSMs, custom instruction decoders, and waveform generators. With JTAG ISP the design can be revised without depopulation, and the industrial temperature rating suits factory-floor retrofits. Engineers migrating from GAL22V10 or PALCE16V8 designs should leverage Altera's MAX+PLUS II or Quartus II legacy mode for direct import.
Recommended
Automotive Body Electronics
In automotive body-control modules the EPM3128ATI144-10 handles load-driver multiplexing, bulb-out detection, and LIN/CAN bus wake-up logic. The 3.3-V core with 5-V-tolerant I/O interfaces directly to 12-V automotive battery rails via external transceivers. Industrial temperature grade (-40C to +85C) covers under-hood and cabin environments. Note: this part is NOT AEC-Q100 qualified; for safety-critical or powertrain applications use a dedicated automotive CPLD such as the MAX II automotive variant. The JTAG ISP enables end-of-line programming during vehicle assembly.
Recommended
Recommended Products Summary
Engineering reference data for EPM3128ATI144-10 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM3128ATC144-10N | EPM3128ATC144-10 | EPM3128ATC144-7N | EPM3128ATC144-5N | EPM3128ATC144-7 |
|---|---|---|---|---|---|---|
| Brand | Altera / Intel | Altera / Intel | Altera / Intel | Altera / Intel | Altera / Intel | Altera / Intel |
| Package | TQFP-144 (FINE LINE) | TQFP-144 (FINE LINE) - same | TQFP-144 (FINE LINE) - same | TQFP-144 (FINE LINE) - same | TQFP-144 (FINE LINE) - same | TQFP-144 (FINE LINE) - same |
| Family | MAX 3000A | MAX 3000A | MAX 3000A | MAX 3000A | MAX 3000A | MAX 3000A |
| Macro Cells | 128 | 128 | 128 | 128 | 128 | 128 |
| Speed Grade | -10 (10 ns pin-to-pin) | -10 (10 ns) | -10 (10 ns) | -7 (~7 ns, faster) | -5 (~5 ns, fastest) | -7 (~7 ns, faster) |
| Operating Temperature | -40C to +85C (Industrial) | 0C to +70C (Commercial) | 0C to +70C (Commercial) | 0C to +70C (Commercial) | 0C to +70C (Commercial) | 0C to +70C (Commercial) |
| Counter Frequency | 98 MHz typical | 98 MHz | 98 MHz | 192.3 MHz (higher) | 227.3 MHz (highest) | 192.3 MHz (higher) |
| User I/Os | 98 | 98 | 98 | 98 | 98 | 98 |
| Lifecycle Status | NRND | NRND | NRND | NRND | NRND | NRND |
Key Differentiators
- Industrial temperature range (-40C to +85C) (vs EPM3128ATC144-10N)
- Standard -10 speed grade with 98 MHz counter frequency (vs XC9572XL-10TQG144I (Xilinx))
- PCI 2.2 compliant I/O buffers in -10 speed grade (vs EPM240T100C5N (MAX II))
Design Notes
The EPM3128ATI144-10 requires a clean 3.3-V VCCINT rail. Place a 10 uF bulk tantalum or ceramic capacitor near the package and at least six 0.1 uF ceramic decoupling capacitors distributed around the VCCINT/VCCIO pin pairs (per the MAX 3000A reference design). Estimated: Icore is approximately 30 mA quiescent, rising to 80-120 mA with high-frequency logic activity. A low-noise LDO such as the TPS7A4533 or LM1117-3.3 is recommended for noise-sensitive analog-adjacent designs. Do not power the device from a switching converter without adequate output filtering, as supply ripple couples directly into I/O thresholds.
For the 144-pin TQFP (FINE LINE), use a 4-layer PCB with a continuous ground plane on layer 2 beneath the device. Route JTAG signals (TCK, TMS, TDI, TDO) on the top layer directly to a 4-pin or 10-pin JTAG header with no stubs. Maintain 50-ohm characteristic impedance on TCK if it exceeds 50 mm. Keep high-speed I/O traces short (<50 mm) and use a ground guard via fence on either side of clock and output-enable traces to reduce crosstalk. The exposed thermal pad (if present on this TQFP variant) should be soldered to a 5x5 mm copper pour connected to GND.
Do not confuse the EPM3128ATI144-10 (industrial temperature, -40C to +85C) with the EPM3128ATC144-10 (commercial 0C to +70C) - the part marking 'I' vs 'C' after 'TI144' is the only visual differentiator on the top marking. Both share the same JTAG IDCODE, so a Quartus II programmer will program either one; verify your inventory and BOM carefully. Do not exceed the 3.6-V absolute-maximum VCCINT rating - the device does NOT have 5-V tolerance on VCCINT, only on selected I/O pins per the datasheet. Finally, ensure the JTAG chain is correctly ordered when multiple devices share the bus; the EPM3128ATI144-10 expects TCK rising-edge sampling and TDI/TDO order per IEEE 1149.1.
Compliance Information
RoHS compliant per lead-free TQFP-144 package. Not AEC-Q100 qualified; not recommended for automotive safety-critical applications without additional qualification. Halogen-free status not explicitly stated in available data - marked unknown.
