EPM9560RI304-15N - 560-Macrocell MAX 9000 CPLD, 15ns, RQ304 | Altera
MPN: EPM9560RI304-15N ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $145 | $145.00 |
| 10 | $132 | $1,320.00 |
| 100 | $115 | $11,500.00 |
| 500 | $99.5 | $49,750.00 |
| 1,000 | $88.75 | $88,750.00 |
Drop-in alternatives for EPM9560RI304-15N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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EPM9560RC304-15N
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View Datasheet →EPM9560RI304-15N Maximum Ratings & Electrical Characteristics
| Family | MAX 9000 |
| Series / Part Number | EPM9560 |
| Device Type | CPLD (EE PLD), in-system programmable, EEPROM-based |
| Macrocells | 560 |
| Flip-Flops | 772 |
| Logic Array Blocks (LABs) | 16 |
| User I/Os | 216 |
| Maximum Internal Frequency | 145 MHz |
| Propagation Delay (pin-to-pin) | 15 ns (speed grade -15) |
| Supply Voltage | 5.0 V core, multi-volt I/O (3.3 V / 5.0 V) |
| Process Technology | High-performance CMOS, EEPROM configuration memory |
| Package | RQFP-304 (HFQFP-304), 1.27 mm gull-wing pitch |
| Pin Count | 304 |
| Operating Temperature (commercial) | 0 C to 70 C |
| Programming Interface | JTAG (IEEE 1532 / IEEE 1149.1) in-system programmable |
| Architecture | Multiple Array MatriX (MAX), third-generation, PIA interconnect |
EPM9560RI304-15N rqfp-304 (hfqfp-304), 1.27 mm gull-wing pitch Pin Configuration Guide
Complete pinout information for EPM9560RI304-15N (rqfp-304 (hfqfp-304), 1.27 mm gull-wing pitch package) with 304 pins. This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EPM9560RI304-15N.
Refer to the datasheet for full pin configuration.
Estimated pin count: 304 pins (digital package)
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM9560RI304-15N is suitable for 6 applications: Industrial Control Glue Logic, Legacy Peripheral Replacement, Bus Address Decoding & Bridging, Rapid State-Machine Prototyping, JTAG-Controlled I/O Expansion, Power-Sequencing & Reset Distribution.
Industrial Control Glue Logic
The EPM9560RI304-15N fits industrial control glue logic because its 560 macrocells and 216 user I/Os provide more than enough capacity to consolidate dozens of 74-series logic chips into a single non-volatile device. The 15 ns pin-to-pin propagation delay supports deterministic address decoding for legacy 8/16/32-bit microprocessor and PLC backplanes, while the 145 MHz internal frequency handles higher-speed control loops. Instant-on EEPROM configuration means the controller boots in defined states without an external boot PROM, critical for safety interlocks. Multi-volt 3.3 V / 5.0 V I/O simplifies bridging between modern MCUs and legacy 5 V peripherals on the same board.
Recommended
Legacy Peripheral Replacement
The EPM9560RI304-15N is a natural choice for legacy peripheral replacement because engineers can map the exact behavior of discontinued TTL/CMOS ASICs and gate arrays into 560 macrocells, retaining pin-compatible behavior with the surrounding system. Its non-volatile EEPROM configuration preserves logic state across power cycles, and JTAG-based IEEE 1532 in-system programmability lets field updates be applied without removing the board. The 304-pin RQFP package (1.27 mm pitch) is compatible with the original through-hole and surface-mount footprints of many late-1990s peripheral ASICs, simplifying board rework.
Recommended
Bus Address Decoding & Bridging
The EPM9560RI304-15N's deterministic 15 ns propagation delay makes it ideal for bus address decoding and bridging between microprocessors, DSPs, and peripherals sharing the same address/data bus. With 216 user I/Os the device can simultaneously decode multiple chip-select windows, latch address lines, and provide registered buffers for ISA, VME, and custom backplanes. The MAX 9000 architecture gives uniform delay across all paths, eliminating skew-induced address glitches. Multi-volt I/O allows direct connection to both 5 V and 3.3 V bus segments without external level shifters.
Recommended
Rapid State-Machine Prototyping
The EPM9560RI304-15N accelerates state-machine prototyping because engineers can iterate HDL designs in MAX+PLUS II or Quartus and program the chip in-circuit via JTAG in seconds. The 772 flip-flops distributed across 560 macrocells support deep FSMs for protocol engines, sequencers, and custom serial controllers. The non-volatile EEPROM configuration means prototypes boot instantly on power-up, simplifying bench bring-up. Once the design is stable the same EPM9560 die can be retargeted to lower-cost MAX 9000 packages for production.
Recommended
JTAG-Controlled I/O Expansion
The EPM9560RI304-15N supports JTAG-controlled I/O expansion because every user I/O can be reconfigured through the IEEE 1149.1 boundary-scan chain, enabling remote digital I/O aggregation in test and instrumentation equipment. The 216 available I/Os let a single CPLD replace multiple shift-register expansion cards. The 15 ns propagation delay supports scan rates above the IEEE 1149.1 TCK maximum with margin, and the multi-volt I/O accommodates 3.3 V and 5.0 V target boards from a single CPLD bank.
Recommended
Power-Sequencing & Reset Distribution
The EPM9560RI304-15N is well-suited to power-sequencing and reset distribution because its instant-on EEPROM configuration produces defined logic states at power-up without external boot logic. The 560 macrocells allow each power rail to be sequenced with its own timer and supervisor comparator logic, while the 216 I/Os handle multiple enable signals, fault flags, and watchdog inputs. The 5 V core and multi-volt I/O mate directly with mixed-voltage power trees in servers, networking gear, and industrial controllers.
Recommended
Recommended Products Summary
Engineering reference data for EPM9560RI304-15N — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9560RC304-15N | EPM9560RC304-15 | EPM9560RC304-15C | EPM9560RC304-20N | EPM9560RC304-10 |
|---|---|---|---|---|---|---|
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Package | RQFP-304 (HFQFP-304) | RQFP-304 - same | RQFP-304 - same | RQFP-304 - same | RQFP-304 - same | RQFP-304 - same |
| Macrocells | 560 | 560 | 560 | 560 | 560 | 560 |
| Flip-Flops | 772 | 772 | 772 | 772 | 772 | 772 |
| User I/Os | 216 | 216 | 216 | 216 | 216 | 216 |
| Propagation Delay | 15 ns | 15 ns | 15 ns | 15 ns | 20 ns | 10 ns |
| Max Internal Frequency | 145 MHz | 145 MHz | 145 MHz | 145 MHz | [DATA_NEEDED] | [DATA_NEEDED] |
| Supply Voltage | 5.0 V core, 3.3/5.0 V I/O | 5.0 V core, 3.3/5.0 V I/O | 5.0 V core, 3.3/5.0 V I/O | 5.0 V core, 3.3/5.0 V I/O | 5.0 V core, 3.3/5.0 V I/O | 5.0 V core, 3.3/5.0 V I/O |
| Temperature Grade | Commercial (0 to 70 C) | Commercial | Commercial | Commercial | Commercial | Commercial |
Key Differentiators
- Higher macrocell count than MAX 7000 family (vs EPM7256SRC208-10N)
- Largest I/O count of any MAX 9000 RQFP-304 part (vs EPM9560RI240-15N)
- Multi-volt I/O bridges 3.3 V and 5.0 V on one die (vs EPM9480RC208-15)
- Faster speed grade available in same package (vs EPM9560RC304-20N)
Design Notes
Estimated: the EPM9560RI304-15N draws ICC in tens of mA when quiescent and rises with toggle rate; at 100% I/O toggle into a 50 pF load, Icco contribution can exceed 200 mA. Place one 0.1 uF X7R bypass per VCC/VCCIO pin pair and a single 10-47 uF bulk tantalum or ceramic near the package. For mixed 3.3 V / 5.0 V I/O banks, dedicate a separate ferrite or LC filter to each VCCIO rail to suppress switching noise coupling into analog sections.
Use a 4-layer PCB with continuous ground and power planes under the RQFP-304 footprint. The 304-pin 1.27 mm gull-wing package has long leads and high inductance; escape the inner rows with short vias to inner planes, and keep JTAG signals (TCK, TMS, TDI, TDO, TRST) routed away from high-edge-rate clocks. Match clock trace lengths to within 200 mil for registered I/O timing closure. Add 4-6 thermal vias under the package center pad (if exposed) to spread heat into the inner ground plane.
Do not assume JTAG IDs are unique across MAX 9000 variants - share the JTAG chain carefully with other boundary-scan devices, and verify TCK termination if the chain exceeds 8 inches. Do not exceed 5.0 V on any I/O pin configured for 3.3 V operation, even momentarily during hot-plug. Finally, ensure the MAX+PLUS II or Quartus MAX device support file is loaded before compiling - missing support files are the most common reason for 'device not supported' errors on legacy MAX 9000 designs.
Place the EPM9560RI304-15N within 2 inches of the bus or microprocessor it decouples to keep address-decode propagation delays within the 15 ns budget. Series-terminate clock outputs with 33-68 ohm resistors when driving more than 2 inches of microstrip, and reference the termination resistor to the receiver end. For multi-CPLD boards, fan JTAG through a 4-wire daisy chain or star topology; avoid stubs on TCK greater than 0.5 inch.
Compliance Information
Lead-free per 'N' suffix in Altera ordering scheme. RoHS, REACH, halogen-free, and conflict-mineral status for EPM9560RI304-15N specifically not stated in the Verified Web Data and left as [DATA_NEEDED] / unknown.
