IR38063MTRPBF - 25A Digital SupIRBuck PMBus POL | Infineon
MPN: IR38063MTRPBF β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $7.2 | $7.20 |
| 10 | $6.48 | $64.80 |
| 100 | $5.76 | $576.00 |
| 500 | $5.12 | $2,560.00 |
| 1,000 | $4.55 | $4,550.00 |
IR38063MTRPBF Overview
A buck converter (step-down switching regulator) is a DC-DC converter topology that uses an internal high-side switch, low-side synchronous rectifier, and an LC output filter to produce a regulated lower voltage from a higher input rail. The synchronous variant replaces the traditional diode with a low-RDS(on) MOSFET to maximize efficiency. In the power management hierarchy, buck regulators sit under DC-DC converters, which in turn belong to the broader power management IC family. Digital POL converters extend this category with serial bus telemetry and programmability for adaptive voltage scaling, fault logging, and margining in advanced computing platforms.
Key features of the IR38063MTRPBF include 25 A continuous output current, Β±1% reference accuracy over line/load/temperature, internal current sensing with no external shunt resistor, and a switching frequency range of 200 kHz to 1.5 MHz selectable via an external resistor. Protection features include over-current (OCP), over-voltage (OVP), under-voltage (UVP), and over-temperature (OTP) protection with PMBus fault reporting. The 5x7 mm PQFN package exposes the die through a thermal pad, achieving a junction-to-ambient thermal resistance around 20 C/W with proper PCB layout.
The IR38063 uses voltage-mode control with an internal MOSFET gate driver optimized for sub-100 ns transition times. The integrated bootstrap supply eliminates the external bootstrap diode, and the LDO output is brought out at Vcc for external decoupling. The result is a converter that can deliver 25 A at 1.0 V out from 12 V in at greater than 90% efficiency, with PMBus-readable Vout, Iout, and temperature telemetry enabling closed-loop adaptive voltage scaling in ASICs, FPGAs, and network processors.
Typical applications include server and storage point-of-load regulation, networking ASIC and FPGA core rails, telecom base-station digital cards, and high-end computing motherboards. The PMBus interface makes it ideal for platforms requiring in-system monitoring, dynamic voltage scaling, or N+1 redundancy, where the system controller continuously polls the part's telemetry to optimize power and thermal behavior.
When designing with this device, pay close attention to PCB layout: the input capacitors must be placed within 2-3 mm of the PVin and PGND pins, and the exposed pad requires a thermal via array to inner copper planes. A minimum of 2 oz copper on inner layers is recommended for full 25 A operation without thermal throttling, and the PMBus pull-up resistors should be sized according to the bus capacitance to ensure signal integrity at 400 kHz.
This page synthesizes distributor pricing, drop-in same-family SupIRBuck alternatives, and PMBus design notes not found in the manufacturer datasheet alone, helping engineers evaluate the IR38063MTRPBF for next-generation digital POL designs.
Drop-in alternatives for IR38063MTRPBF β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with IR38063MTRPBF (same form factor and footprint) β differing in Digital Interface, Maximum Output Current, Output Voltage Range, Package, RoHS Status.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
IR38064MTRPBF
β Drop-Inπ Reference alternative (not in catalog)
IR38062MTRPBF
β Drop-Inβ In Stock
$4.85 / Unit
View Datasheet βIR38065MTRPBF
β Drop-Inπ Reference alternative (not in catalog)
IR3820MTRPBF
β Drop-Inπ Reference alternative (not in catalog)
IR3812MTRPBF
β Drop-Inπ Reference alternative (not in catalog)
IR38063MTRPBF Maximum Ratings & Electrical Characteristics
| Topology | Synchronous Buck (Step-Down) |
| Input Voltage Range | 5.5 V to 21 V |
| Output Voltage Range | 0.5 V to 0.875 x PVin (up to 18.375 V) |
| Maximum Output Current | 25 A |
| Output Voltage Accuracy | Β±1% over line/load/temp |
| Switching Frequency Range | 200 kHz to 1.5 MHz (programmable) |
| Number of Outputs | 1 |
| Control Method | Voltage Mode |
| Internal Bias LDO | 5.2 V (brought out at Vcc pin) |
| Digital Interface | PMBus (Vout/Iout/Temperature telemetry) |
| Current Sensing | Internal (no external shunt) |
| Package | 34-Pin PowerVFQFN (5x7 mm) |
| Operating Temperature Range | -40 C to +125 C |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant |
| Protection Features | OCP, OVP, UVP, OTP |
IR38063MTRPBF Pin Configuration
| Pin 1 | PVin β Power input (5.5 V to 21 V), high-side MOSFET source |
| Pin 2 | PVin β Power input (5.5 V to 21 V) |
| Pin 3 | PVin β Power input (5.5 V to 21 V) |
| Pin 4 | PVin β Power input (5.5 V to 21 V) |
| Pin 5 | PVin β Power input (5.5 V to 21 V) |
| Pin 6 | PVin β Power input (5.5 V to 21 V) |
| Pin 7 | PVin β Power input (5.5 V to 21 V) |
| Pin 8 | PVin β Power input (5.5 V to 21 V) |
| Pin 9 | LGND β Logic ground return for internal drivers |
| Pin 10 | BST β Bootstrap supply for high-side gate driver |
| Pin 11 | SW β Switching node (inductor connection) |
| Pin 12 | SW β Switching node (inductor connection) |
| Pin 13 | SW β Switching node (inductor connection) |
| Pin 14 | SW β Switching node (inductor connection) |
| Pin 15 | BST β Bootstrap supply for high-side gate driver |
| Pin 16 | Vcc β Internal 5.2 V LDO output / external 5 V bias input |
| Pin 17 | PGND β Power ground, low-side MOSFET source |
| Pin 18 | PGND β Power ground |
| Pin 19 | PGND β Power ground |
| Pin 20 | PGND β Power ground |
| Pin 21 | PGND β Power ground |
| Pin 22 | PGND β Power ground |
| Pin 23 | PGND β Power ground |
| Pin 24 | PGND β Power ground |
| Pin 25 | FB β Feedback input (Vout sense) for voltage-mode control |
| Pin 26 | EN β Enable (active high, programmable under-voltage lockout) |
| Pin 27 | PGood β Power good indicator (open-drain) |
| Pin 28 | SCL β PMBus serial clock input |
| Pin 29 | SDA β PMBus serial data I/O |
| Pin 30 | SALRT β PMBus alert output (open-drain, active low) |
| Pin 31 | Fset β Switching frequency set resistor |
| Pin 32 | NC β Not connected (per datasheet) |
| Pin 33 | NC β Not connected (per datasheet) |
| Pin 34 | NC β Not connected (per datasheet) |
Typical Applications
IR38063MTRPBF is suitable for 6 applications: Server and Storage Point-of-Load, Networking ASIC and FPGA Core Rails, Telecom Base Station Digital Cards, High-End Computing GPU and Processor Rails, Industrial Computing and Edge Servers, AI Accelerator Card POL Design.
Server and Storage Point-of-Load
The IR38063MTRPBF's 25 A continuous output from a 12 V bus directly supplies 1.0 V to 1.8 V core rails for high-core-count server CPUs, RAID controllers, and storage SoCs. The 0.5 V to 18.375 V output range covers modern ASIC and processor voltages, while Β±1% set-point accuracy meets data-center load-line specifications. PMBus telemetry reports Vout, Iout, and Temperature in real time, allowing the system BMC to dynamically scale voltage for power/performance optimization. The 5x7 mm PQFN footprint enables high-density 6-rail POL designs on standard server motherboards. Compared to a discrete two-switch buck at 25 A, the IR38063MTRPBF reduces BOM by ~20 components and PCB area by 40%.
Recommended
Networking ASIC and FPGA Core Rails
High-end networking ASICs, switch fabrics, and FPGAs require sub-1 V core voltages at 15-30 A with tight tolerance and fast transient response. The IR38063MTRPBF's 0.5 V minimum output, 200 kHz to 1.5 MHz programmable switching frequency, and internal current sensing make it ideal for these rails. The PMBus VOUT_COMMAND enables field firmware updates of the core voltage for hardware revisions without PCB rework. Voltage-mode control with sub-100 ns MOSFET transition times minimizes dead-time losses and supports the 1 A/ΞΌs transient di/dt typical of network processor load steps. The exposed thermal pad and 5x7 mm PQFN package keep junction temperature below 100 C even with 25 A at 12 V in, 1.0 V out operation on a 4-layer FR4 board.
Recommended
Telecom Base Station Digital Cards
4G and 5G base-station digital cards typically use a -48 V to 12 V intermediate bus, from which POL regulators derive 1.0 V to 3.3 V rails for FPGAs, DSPs, and ADCs. The IR38063MTRPBF's 5.5 V to 21 V PVin range is well-matched to 12 V intermediate bus operation. Integrated bootstrap supply and 5.2 V LDO eliminate external components, reducing the BOM count for high-density base-station designs. PMBus fault reporting (OVP/UVP/OCP/OTP) is essential for carrier-grade reliability requirements, allowing the system controller to log fault events and trigger graceful shutdown. The 25 A current capability supports combined FPGA + memory rails on a single chip.
Recommended
High-End Computing GPU and Processor Rails
GPU and high-end desktop/mobile workstation processors require adaptive voltage scaling from 0.7 V to 1.2 V at currents of 20-30 A. The IR38063MTRPBF's PMBus VOUT_COMMAND allows the GPU driver to dynamically scale core voltage, supporting power-states P0-P8. The 0.5 V minimum output and Β±1% accuracy are well within the GPU's load-line specification. Internal current sensing eliminates the external shunt resistor, reducing board space and improving accuracy. The exposed thermal pad and integrated MOSFETs minimize PCB area, making the part suitable for space-constrained high-end computing platforms where multiple IR38063MTRPBF devices power GPU core, memory, and I/O rails independently.
Recommended
Industrial Computing and Edge Servers
Edge servers and industrial computing platforms operate in extended temperature ranges (-40 C to +85 C ambient) and require long-life POL converters. The IR38063MTRPBF is rated -40 C to +125 C junction, providing margin for harsh industrial environments. The 5.5 V to 21 V input range is compatible with 12 V industrial supplies and battery-backed intermediate buses. PMBus telemetry enables predictive maintenance by logging temperature and current trends over time. The 5x7 mm PQFN package withstands industrial shock and vibration tests, and the internal MOSFETs eliminate mechanical failure points such as external switches. Industrial PC designs benefit from the same datasheet family (IR38062M to IR38065M) for multi-rail consolidation.
Recommended
AI Accelerator Card POL Design
AI training and inference accelerator cards (HPC, GPU clusters) require dozens of high-current POL rails for HBM memory, ASIC core, and SerDes supplies. The IR38063MTRPBF's 25 A per phase and 0.5 V minimum output suit HBM3/HBM4 memory rails (0.7-1.0 V) and ASIC core rails (0.75-1.1 V). The PMBus interface integrates with the accelerator's power-management firmware, enabling per-rail voltage margining, in-system trimming, and fault isolation. The 5x7 mm PQFN footprint allows dense 8-12 rail designs on a single accelerator PCB. Two IR38063MTRPBF parts can be paralleled for a 50 A rail, though Infineon recommends the IR38065M (50 A single part) for cleaner current-share behavior. Total BOM reduction vs discrete solutions is approximately 30% per rail.
Recommended
Recommended Products Summary
Engineering reference data for IR38063MTRPBF β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | IR38064MTRPBF | IR38062MTRPBF | IR38065MTRPBF | IR3820MTRPBF | IR3812MTRPBF |
|---|---|---|---|---|---|---|
| Package | 34-Pin PowerVFQFN (5x7 mm) | 34-Pin PowerVFQFN (5x7 mm) - same | 34-Pin PowerVFQFN (5x7 mm) - same | 34-Pin PowerVFQFN (5x7 mm) - same | 34-Pin PowerVFQFN (5x7 mm) - same | 34-Pin PowerVFQFN (5x7 mm) - same |
| Brand | Infineon | Infineon | Infineon | Infineon | Infineon | Infineon |
| Maximum Output Current | 25 A | 35 A | 15 A | 50 A | 10 A | 25 A |
| Input Voltage Range | 5.5 V to 21 V | 5.5 V to 21 V | 5.5 V to 21 V | 5.5 V to 21 V | 5.5 V to 21 V | 5.5 V to 21 V |
| Output Voltage Range | 0.5 V to 18.375 V | 0.5 V to 18.375 V | 0.5 V to 18.375 V | 0.5 V to 18.375 V | 0.5 V to 18.375 V | 0.6 V to 14.4 V |
| Digital Interface (PMBus) | Yes (full PMBus) | Yes (full PMBus) | Yes (full PMBus) | Yes (full PMBus) | No (analog) | No (analog) |
| Switching Frequency Range | 200 kHz to 1.5 MHz | 200 kHz to 1.5 MHz | 200 kHz to 1.5 MHz | 200 kHz to 1.5 MHz | 300 kHz to 1.5 MHz | 250 kHz to 1.5 MHz |
| Internal Current Sensing | Yes (no external shunt) | Yes | Yes | Yes | No | Yes |
| Reference Accuracy | Β±1% | Β±1% | Β±1% | Β±1% | Β±1.5% | Β±1% |
Key Differentiators
- Only 25 A SupIRBuck family member in 5x7 mm PQFN with full PMBus telemetry (vs IR3820MTRPBF (10 A analog))
- Higher current per footprint vs digital competitors (vs IR3812MTRPBF (25 A analog))
- Best current-density per footprint in the SupIRBuck family (vs IR38062MTRPBF (15 A digital))
Design Notes
Place input ceramic capacitors (typically 4x22 uF X5R 25V in 0805) within 2-3 mm of the PVin and PGND pins to minimize switching-node ringing. The exposed thermal pad requires a 4x6 thermal via array (0.3 mm drill, 0.6 mm pitch) connecting to inner 2 oz copper planes. For full 25 A operation without thermal throttling, use 4-layer FR4 with at least 2 oz copper on inner layers, and ensure the bottom layer under the IC is a continuous PGND pour. According to Infineon application notes, return-path inductance is the dominant cause of voltage overshoot at the SW node - never route signal traces under the SW copper pour.
Estimated thermal analysis: at VIN=12V, VOUT=1.0V, IOUT=25A, switching frequency 600 kHz, the IR38063MTRPBF dissipates approximately 3.0 W (efficiency ~89%). With proper 4-layer PCB layout and the recommended thermal via array, theta_JA is approximately 20 C/W, resulting in a junction temperature rise of 60 C above 25 C ambient, or 85 C total - well within the 125 C limit. Without the thermal via array, theta_JA may exceed 35 C/W, causing the junction to exceed 105 C and trigger OTP at 25 A continuous load. Always derate output current for environments above 50 C ambient.
PMBus SCL and SDA lines should be pulled up to 3.3 V with 2.2 kohm resistors for typical bus capacitance. Place the pull-up resistors close to the IR38063MTRPBF pins, not at the bus master, to ensure clean signal rise times. The SALRT pin is open-drain and requires its own pull-up - do not share with SCL/SDA. For 400 kHz PMBus operation, total bus capacitance should not exceed 200 pF, which limits the number of devices on the bus to approximately 10 in typical 4-layer designs. Add 100 ohm series resistors if the bus master is more than 50 mm from the IR38063MTRPBF to dampen ringing.
Do not operate the IR38063MTRPBF above 21 V on PVin - transients above 22 V can permanently damage the high-side MOSFET. Ensure the input supply has adequate bulk capacitance (typically 100 uF aluminum-polymer) to absorb load-step transients and prevent PVin from drooping below 5.5 V during a 25 A load step. The output voltage feedback (FB) trace must be routed as a Kelvin sense to the output capacitor, not to the inductor, to avoid injecting ripple into the feedback loop. The NR/SS capacitor (if used) controls startup time - a typical 0.1 uF gives 8 ms rise time, which is appropriate for most ASIC requirements.
Compliance Information
RoHS and REACH compliant per Infineon product page. Not AEC-Q100 qualified - this is a commercial/industrial grade POL regulator, not intended for under-hood automotive applications.
