MC68882EI25AR - 25MHz 68882 FPU Co-Processor | 68-PLCC
MPN: MC68882EI25AR ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $69.7 | $69.70 |
| 10 | $65.5 | $655.00 |
| 100 | $60 | $6,000.00 |
| 500 | $54.5 | $27,250.00 |
| 1,000 | $49 | $49,000.00 |
MC68882EI25AR Overview
An FPU co-processor is a specialized processor that works in lockstep with a host CPU to execute floating-point instructions in hardware rather than emulating them in software. Within the M68000 ecosystem hierarchy, the MC68882 sits beside the host CPU as an M-class co-processor (companion chip), falling under the broader categories of math co-processor -> co-processor -> specialized IC -> microprocessor peripheral. By handling transcendental functions (sine, cosine, log, exp), IEEE 754 arithmetic, and packed BCD, the 68882 delivered workstation-class numeric performance to 68k-based systems such as the Amiga, Atari, early Macintosh, and various industrial/embedded controllers.
Key features include hardware IEEE 754 single and double precision, eight 80-bit floating-point registers organized as a stack with renaming, fully concurrent execution with the host CPU through the M68000 coprocessor interface, and support for the complete M68000 family F-line instruction set including FMOV, FADD, FMUL, FDIV, FSIN, FCOS, FLOG and FEXP. The 25 MHz suffix (-25) corresponds to a 25 MHz system-clock operation. The PLCC-68 surface-mount package retains the traditional J-lead footprint for easy socket replacement on legacy boards.
The 68882 architecture consists of an instruction-decoder/prefetch unit, an FPU execution datapath, an 80-bit register file, and a bus interface that communicates with the host CPU through the M68000 coprocessor protocol. Unlike modern integrated FPUs, the 68882 occupies a separate socket and is invisible to software once configured - the host CPU decodes F-line opcodes and dispatches them to the co-processor transparently. Internal pipeline overlap allows the host and FPU to run concurrently, hiding latency.
Typical applications include legacy M68020/M68030 workstation upgrades (Amiga 3000/4000, Atari TT/Falcon, early Mac II/Quadra via PDS cards), industrial-control retrofit boards requiring floating-point acceleration, vintage computer restoration projects, and educational/emulation environments studying 68k architecture. Because the part is now in the obsolete/EOL category, it is most often sourced for maintenance of installed bases rather than new design.
A key design consideration when working with this part is that the 68882 must be clocked at the same frequency as, or in lockstep with, the host M68000 CPU; mismatch causes timing violations on the coprocessor handshake. Because the part is obsolete, second-source and franchised stocking distributors are the primary supply channel. Designers should always verify lot traceability and request a manufacturer certificate of conformance when procuring.
This page synthesizes current distributor pricing, parametric comparison with same-family variants, and practical sourcing/design notes not found in the original Motorola/NXP datasheet alone.
Drop-in alternatives for MC68882EI25AR — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with MC68882EI25AR (same form factor and footprint) — differing in Mounting Type, Floating-Point Standard, Function, Operating Frequency, Package / Case.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
MC68882EI16A
✅ Drop-In✓ In Stock
$36.94 / Unit
View Datasheet →MC68882EI20A
✅ Drop-In✓ In Stock
$38.1 / Unit
View Datasheet →MC68882EI33A
✅ Drop-In📋 Reference alternative (not in catalog)
MC68882EI40A
✅ Drop-In📋 Reference alternative (not in catalog)
MC68882EI25AR Maximum Ratings & Electrical Characteristics
| Part Status | Obsolete |
| Type | Floating-Point Co-Processor |
| Series | MC680x0 |
| Nominal Supply Voltage | 5 V |
| Maximum Supply Voltage | 5.25 V |
| Minimum Supply Voltage | 4.75 V |
| Operating Frequency | 25 MHz |
| Maximum Operating Temperature | 70 C |
| Temperature Grade | Commercial |
| Package / Case | 68-LCC (J-Lead) |
| Supplier Device Package | 68-PLCC (24.21 x 24.21 mm) |
| Mounting Type | Surface Mount |
| Terminal Finish | Matte Tin |
| Host CPU Compatibility | MC68020, MC68030, MC68040 |
| Floating-Point Standard | IEEE 754 (single & double precision, 80-bit extended) |
| Application | Math co-processor for 68k family |
MC68882EI25AR Pin Configuration
| Pin 1 | GND — Ground |
| Pin 2 | DSACK0 — Data transfer and size acknowledge 0 |
| Pin 3 | DSACK1 — Data transfer and size acknowledge 1 |
| Pin 4 | AVEC — Autovector interrupt request |
| Pin 5 | IPL0 — Interrupt priority level 0 |
| Pin 6 | IPL1 — Interrupt priority level 1 |
| Pin 7 | IPL2 — Interrupt priority level 2 |
| Pin 8 | VCC — +5 V supply |
| Pin 9 | GND — Ground |
| Pin 10 | BGND — Bus grant (debug) |
| Pin 11 | BR — Bus request |
| Pin 12 | BG — Bus grant |
| Pin 13 | RMC — Read-modify-write cycle |
| Pin 14 | SIZ0 — Transfer size bit 0 |
| Pin 15 | SIZ1 — Transfer size bit 1 |
| Pin 16 | FC0 — Function code bit 0 |
| Pin 17 | FC1 — Function code bit 1 |
| Pin 18 | FC2 — Function code bit 2 |
| Pin 19 | A0 — Address bus bit 0 |
| Pin 20 | A1 — Address bus bit 1 |
| Pin 21 | A2 — Address bus bit 2 |
| Pin 22 | A3 — Address bus bit 3 |
| Pin 23 | A4 — Address bus bit 4 |
| Pin 24 | A5 — Address bus bit 5 |
| Pin 25 | A6 — Address bus bit 6 |
| Pin 26 | A7 — Address bus bit 7 |
| Pin 27 | A8 — Address bus bit 8 |
| Pin 28 | A9 — Address bus bit 9 |
| Pin 29 | A10 — Address bus bit 10 |
| Pin 30 | A11 — Address bus bit 11 |
| Pin 31 | A12 — Address bus bit 12 |
| Pin 32 | A13 — Address bus bit 13 |
| Pin 33 | A14 — Address bus bit 14 |
| Pin 34 | A15 — Address bus bit 15 |
| Pin 35 | A16 — Address bus bit 16 |
| Pin 36 | A17 — Address bus bit 17 |
| Pin 37 | A18 — Address bus bit 18 |
| Pin 38 | A19 — Address bus bit 19 |
| Pin 39 | A20 — Address bus bit 20 |
| Pin 40 | A21 — Address bus bit 21 |
| Pin 41 | A22 — Address bus bit 22 |
| Pin 42 | A23 — Address bus bit 23 |
| Pin 43 | A24 — Address bus bit 24 |
| Pin 44 | A25 — Address bus bit 25 |
| Pin 45 | A26 — Address bus bit 26 |
| Pin 46 | A27 — Address bus bit 27 |
| Pin 47 | A28 — Address bus bit 28 |
| Pin 48 | A29 — Address bus bit 29 |
| Pin 49 | A30 — Address bus bit 30 |
| Pin 50 | A31 — Address bus bit 31 |
| Pin 51 | D0 — Data bus bit 0 |
| Pin 52 | D1 — Data bus bit 1 |
| Pin 53 | D2 — Data bus bit 2 |
| Pin 54 | D3 — Data bus bit 3 |
| Pin 55 | D4 — Data bus bit 4 |
| Pin 56 | D5 — Data bus bit 5 |
| Pin 57 | D6 — Data bus bit 6 |
| Pin 58 | D7 — Data bus bit 7 |
| Pin 59 | D8 — Data bus bit 8 |
| Pin 60 | D9 — Data bus bit 9 |
| Pin 61 | D10 — Data bus bit 10 |
| Pin 62 | D11 — Data bus bit 11 |
| Pin 63 | D12 — Data bus bit 12 |
| Pin 64 | D13 — Data bus bit 13 |
| Pin 65 | D14 — Data bus bit 14 |
| Pin 66 | D15 — Data bus bit 15 |
| Pin 67 | CLK — System clock input (25 MHz) |
| Pin 68 | VCC — +5 V supply |
Typical Applications
MC68882EI25AR is suitable for 6 applications: Amiga 3000/4000 FPU Upgrade, Atari TT/Falcon FPU Acceleration, Industrial 68k Control Retrofit, Vintage Computer Restoration, Educational / Emulator Development Platform, Legacy Aerospace / Defense Test Equipment.
Amiga 3000/4000 FPU Upgrade
The MC68882EI25AR at 25 MHz pairs directly with the Amiga 3000 and 4000's MC68030 host CPU through the 68k coprocessor interface, delivering IEEE 754 single/double/extended precision in hardware for ray-traced rendering, fractal generation, and audio DSP. At matched 25 MHz clock, the 68882 completes a double-precision multiply in roughly 5 cycles while the host runs concurrently, a substantial speed-up over software FPU emulation on a bare 68030. Designers must place the PLCC-68 socket within 50 mm of the host CPU to keep coprocessor-handshake timing within spec.
Recommended
Atari TT/Falcon FPU Acceleration
Atari TT030 and Falcon030 workstations used the MC68882EI25AR as a drop-in FPU companion to the 68030 host, accelerating CAD/CAM, desktop publishing, and DSP workloads on the 68k platform. The 25 MHz grade was the standard FPU option for the TT030 in PLCC-68 form factor. Installing the part into the dedicated coprocessor socket adds IEEE 754 hardware without firmware changes; the TOS operating system transparently dispatches F-line opcodes to the 68882 as soon as the host detects it during POST.
Recommended
Industrial 68k Control Retrofit
Long-lifecycle industrial controllers based on the MC68020 or MC68030 often retained the MC68882EI25AR for hardware floating-point servo-loop math, where integer-only control would have required excessive software overhead. The commercial 0C to +70C grade is suitable for enclosed control cabinets. Because the part is obsolete, retrofit boards typically source verified stock from franchised distributors such as Rochester Electronics to keep installed-base equipment operational for 10 to 20 additional years.
Recommended
Vintage Computer Restoration
The MC68882EI25AR is a frequent replacement part for restoring vintage 68k workstations, particularly Apple Macintosh II/Quadra logic boards via PDS-card-hosted sockets and early Sun 3 NPU upgrades. Because new-old stock and tested pulls command premium pricing, restoration communities typically match date codes and lot numbers when sourcing. The PLCC-68 J-lead package allows hobbyists to socket the part and avoid repeated soldering during diagnostics.
Recommended
Educational / Emulator Development Platform
Universities and open-source emulator projects (such as ARAnyM, Hatari, and Basilisk II) target the MC68882EI25AR because it represents the canonical 68k FPU to emulate for cycle-accurate behavior. The 25 MHz grade is the most commonly documented timing reference in published 68k FPU performance literature. Including a verified 68882 in a hardware-emulation test rig allows emulator authors to cross-check edge cases (denormals, NaN propagation, rounding modes) against real silicon behavior.
Recommended
Legacy Aerospace / Defense Test Equipment
Some 1990s-vintage aerospace ground-test racks retain 68k processors with the MC68882EI25AR for floating-point signal-processing math (radar return simulation, FFT preprocessing). These programs run on long support timelines (20+ years) and rely on the franchised aftermarket to sustain installed equipment. Procurement specifications require traceability to the original Motorola lot, certificate of conformance, and 100 percent pre-screening on a 68k development board before deployment.
Recommended
Recommended Products Summary
Engineering reference data for MC68882EI25AR — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | MC68882EI16A | MC68882EI20A | MC68882EI33A | MC68882EI40A |
|---|---|---|---|---|---|
| Package | 68-PLCC (J-Lead) | 68-PLCC (J-Lead) | 68-PLCC (J-Lead) | 68-PLCC (J-Lead) | 68-PLCC (J-Lead) |
| Brand | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors |
| Operating Frequency | 25 MHz | 16 MHz | 20 MHz | 33 MHz | 40 MHz |
| Supply Voltage | 5 V (4.75 V to 5.25 V) | 5 V (4.75 V to 5.25 V) | 5 V (4.75 V to 5.25 V) | 5 V (4.75 V to 5.25 V) | 5 V (4.75 V to 5.25 V) |
| Temperature Grade | Commercial (0C to +70C) | Commercial (0C to +70C) | Commercial (0C to +70C) | Commercial (0C to +70C) | Commercial (0C to +70C) |
| Floating-Point Standard | IEEE 754 single/double/extended | IEEE 754 single/double/extended | IEEE 754 single/double/extended | IEEE 754 single/double/extended | IEEE 754 single/double/extended |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
| Host CPU Compatibility | MC68020 / MC68030 / MC68040 | MC68020 / MC68030 / MC68040 | MC68020 / MC68030 / MC68040 | MC68020 / MC68030 / MC68040 | MC68020 / MC68030 / MC68040 |
Key Differentiators
- Balanced clock speed for MC68030 hosts (vs MC68882EI16A)
- Lower power consumption than 33/40 MHz grades (vs MC68882EI33A)
- Commercial temperature range only (vs MC68882RC25A)
Design Notes
Place the MC68882EI25AR within 50 mm of the host MC68030 on the motherboard and keep the coprocessor-handshake traces (DSACK0/1, AVEC, BG, BR, RMC) short and matched in length within 12 mm. The 68882 is sensitive to coprocessor-bus skew; long stubs or excessive capacitive loading cause intermittent FPU detection failures. Use a ground guard trace around the coprocessor bus to limit crosstalk from the host data bus. Decouple each VCC pin with 0.1 uF ceramic plus one shared 10 uF tantalum bulk capacitor.
Drive the CLK pin with a clock source that matches the host MC68030 clock frequency within +/- 100 ppm. Mismatched clocks break the coprocessor handshake protocol and cause the host to time out on F-line instructions. Use a low-jitter clock driver (jitter under 200 ps peak-peak) and place a 33 ohm series-termination resistor near the 68882 CLK pin if the trace exceeds 25 mm. Avoid routing the clock trace over split-plane regions or near switching power-supply nodes.
Do not pair the MC68882EI25AR with an MC68040 host CPU - the 68040 includes an integrated FPU and does not expose the coprocessor interface in a way that supports an external 68882. The most common build error is mounting the part in a PGA-68 socket (which expects the MC68882RC PGA variant) or vice versa. Always verify the suffix: 'EI' means PLCC-68 J-lead, 'RC' means ceramic PGA-68. Both share the same die but require different footprints.
Compliance Information
Matte-tin terminal finish supports lead-free assembly. RoHS compliance reported by distributor channels based on terminal finish; lot-level declarations should be requested from the supplier. REACH, halogen-free, and conflict-minerals status not explicitly published for this obsolete part.
