MPC875ZT133 - PowerQUICC 133MHz 32-Bit MPU | NXP Semiconductors
MPN: MPC875ZT133 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $28.5 | $28.50 |
| 10 | $26.2 | $262.00 |
| 100 | $23.75 | $2,375.00 |
| 500 | $21.4 | $10,700.00 |
| 1,000 | $19.85 | $19,850.00 |
MPC875ZT133 Overview
A PowerQUICC (Power Architecture Quad Integrated Communications Controller) processor is a system-on-chip platform that integrates a high-performance PowerPC core with memory controllers, peripheral interfaces, and dedicated communication engines. It sits within the broader hierarchy of microprocessors -> embedded processors -> communications processors -> SoC, and historically served as the industry-standard building block for routers, switches, DSLAMs, and industrial control before the family was discontinued by NXP/Freescale.
Key specifications include a single 32-bit core, 133 MHz core speed, and the 256-ball PBGA (23x23 mm) surface-mount package with heat-slug/heat-sink slug construction for improved thermal dissipation. Operating voltage is characterized at a 1.9 V maximum rating (per Partstack listing), and the device supports the standard MPC8xx peripheral set including SCCs, SMCs, an SPI, I2C, and a 10/100 Ethernet MAC through the CPM. A PCI interface, memory controller, and dual UART channels round out the on-chip integration.
From an architectural perspective, the MPC875 pairs the PowerPC core with a separate Communications Processor Module (CPM) that handles DMA-driven serial protocols, offloading protocol framing from the core. This dual-engine approach was central to PowerQUICC's value proposition in 1999-2005 era telecom and networking designs, allowing wire-speed processing of multi-channel TDM, Ethernet, and HDLC traffic with low core utilization.
Typical applications include 10/100 Ethernet routers and switches, DSL access multiplexers, ISDN terminal adapters, industrial serial-protocol gateways, and embedded control platforms requiring deterministic multi-channel serial I/O. The 256-PBGA package provides the high pin count needed to expose the external memory bus, PCI, and multiple serial channels simultaneously.
A critical design consideration is that the MPC875ZT133 is now end-of-life per NXP's product discontinuance notice. Long-term designs should evaluate NXP's current PowerQUICC II / QorIQ replacement families, or modern equivalent SoCs from Microchip, which maintain pin-compatibility for many PowerQUICC derivatives and offer current production longevity.
Drop-in alternatives for MPC875ZT133 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with MPC875ZT133 (same form factor and footprint) — differing in Core Architecture, Package, Operating Temperature, Manufacturer, RoHS Status.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
MPC870ZT133
✅ Drop-In✓ In Stock
$28.75 / Unit
View Datasheet →MPC870CZT133
✅ Drop-In✓ In Stock
$71 / Unit
View Datasheet →MPC870VR66
✅ Drop-In✓ In Stock
$25.9 / Unit
View Datasheet →MPC875ZT133 Maximum Ratings & Electrical Characteristics
| Core Architecture | Power Architecture (PowerPC) 32-bit |
| Core Count | 1 |
| Core Frequency | 133 MHz |
| Family | MPC8xx / PowerQUICC |
| Package | 256-ball PBGA (23x23 mm) |
| Package Code | HBGA, Grid Array with Heat Sink/Slug |
| Operating Temperature | 0C to +95C |
| Maximum Supply Voltage | 1.9 V |
| Terminal Form | BALL |
| Number of Terminals | 256 |
| Mounting Type | Surface Mount |
| Communications Processor Module (CPM) | Yes (on-chip) |
| Ethernet MAC | 10/100 Mbps (Fast Ethernet, integrated) |
| Memory Controller | External SDRAM/Flash bus (integrated) |
| Lifecycle Status | End of Life (per NXP discontinuance notice) |
| Instruction Set | Power Architecture 32-bit |
MPC875ZT133 Pin Configuration
| Pin A1 | [DATA_NEEDED: pin name] — PBGA ball A1 - per NXP MPC875 datasheet |
| Pin B5 | [DATA_NEEDED: pin name] — PBGA ball B5 - per NXP MPC875 datasheet |
| Pin C10 | [DATA_NEEDED: pin name] — PBGA ball C10 - per NXP MPC875 datasheet |
| Pin D15 | [DATA_NEEDED: pin name] — PBGA ball D15 - per NXP MPC875 datasheet |
| Pin T16 | [DATA_NEEDED: pin name] — PBGA ball T16 - per NXP MPC875 datasheet |
Typical Applications
MPC875ZT133 is suitable for 6 applications: 10/100 Ethernet Router, DSL Access Multiplexer (DSLAM) Line Card, Industrial Serial-Protocol Bridge, ISDN Terminal Adapter, Embedded Control Platform, Legacy Telecom Base Station Controller.
10/100 Ethernet Router
The MPC875ZT133 fits 10/100 Ethernet router designs because its integrated Fast Ethernet MAC and full Communications Processor Module (CPM) provide wire-speed packet handling at 133 MHz without an external controller. Placed as the main SoC with an external PHY, SDRAM, and flash on the memory controller, it handles routing tables, NAT, and serial WAN protocols via the SCC channels. Trade-off: EOL status means new router designs should evaluate QorIQ successors with active production lifecycles.
Recommended
DSL Access Multiplexer (DSLAM) Line Card
The MPC875ZT133 is suited for DSLAM line card applications where multi-channel serial connectivity from the CPM's SCCs and SMCs handles ATM/HDLC framing over DSL PHY links. At 133 MHz the core can manage multiple subscriber lines concurrently, and the 256-ball PBGA package exposes the wide external memory bus required for cell buffer RAM. Performance benefit: deterministic serial DMA offloads framing from the PowerPC core, freeing it for higher-layer processing.
Recommended
Industrial Serial-Protocol Bridge
Industrial serial-protocol gateways benefit from the MPC875ZT133 because the CPM's multiple SCC channels and integrated I2C/SPI controllers provide simultaneous multi-protocol bridging (Modbus, HDLC, Profibus-style serial) without external UARTs. Operating at 133 MHz the device can manage deterministic real-time serial traffic at high baud rates while the PowerPC core runs application logic. Trade-off: 0C to +95C commercial temperature range means non-climate-controlled enclosures require the MPC870CZT133 industrial variant.
Recommended
ISDN Terminal Adapter
The MPC875ZT133 is well-matched to ISDN terminal adapter designs where its CPM handles the BRI/PRI HDLC channels and the integrated Ethernet MAC provides the LAN-side interface. At 133 MHz it can sustain the channelized TDM rate while running higher-layer PPP, MLP, and IP stacks on the PowerPC core. The 256-ball PBGA's high pin count exposes the full TDM bus and external memory interface needed for buffering.
Recommended
Embedded Control Platform
The MPC875ZT133 works in embedded control platforms requiring deterministic multi-channel serial I/O combined with a 32-bit compute core for application logic. Its integrated memory controller, PCI bridge, dual UART, and CPM-driven serial controllers cover most industrial embedded I/O requirements without external glue logic. At 133 MHz it provides real-time response for control loops while the 256-PBGA supports industrial -40C variants like the MPC870CZT133 in ruggedized deployments.
Recommended
Legacy Telecom Base Station Controller
The MPC875ZT133 historically served as the main processor in legacy 2G/3G telecom base station controllers where its CPM handled Abis interface HDLC framing and the core ran the BSC application stack. Its 133 MHz performance and multi-channel SCC support were adequate for early-generation BSC capacity. Trade-off: the part is EOL, so legacy telecom designs needing spare parts should stock critical inventory or migrate to NXP's current PowerQUICC II successors.
Recommended
Recommended Products Summary
Engineering reference data for MPC875ZT133 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | MPC870ZT133 | MPC870CZT133 | MPC870VR66 |
|---|---|---|---|---|
| Brand | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors |
| Package | 256-ball PBGA (23x23 mm) | 256-ball PBGA (23x23 mm) - same | 256-ball PBGA (23x23 mm) - same | 256-ball PBGA (23x23 mm) - same |
| Core Frequency | 133 MHz | 133 MHz | 133 MHz | 66 MHz (-50%) |
| Operating Temperature | 0C to +95C | 0C to +95C | -40C to +95C (industrial) | 0C to +95C |
| CPM Feature Set | Full PowerQUICC CPM | Reduced CPM (subset) | Reduced CPM (subset) | Reduced CPM (subset) |
| Family | MPC8xx PowerQUICC | MPC8xx PowerQUICC | MPC8xx PowerQUICC | MPC8xx PowerQUICC |
| Core Architecture | PowerPC 32-bit | PowerPC 32-bit | PowerPC 32-bit | PowerPC 32-bit |
| Lifecycle Status | End of Life (EOL) | End of Life (EOL) | End of Life (EOL) | End of Life (EOL) |
Key Differentiators
- Full-featured PowerQUICC CPM with maximum SCC/SMC channel count (vs MPC870ZT133)
- Industrial-temperature variant available in same package (vs MPC870CZT133)
- Higher core speed than lower-cost VR66 grade (vs MPC870VR66)
Design Notes
Estimated - the 256-ball PBGA package incorporates a heat sink/slug (HBGA package code per Partstack) to dissipate the 133 MHz core's thermal output. Estimated power dissipation at 1.9 V maximum supply is approximately 1-1.5 W under typical load. For continuous 100% CPU utilization in a non-airflow enclosure, attach a small clip-on heatsink to the top slug or use thermal vias under the BGA pad pattern. Without active cooling, do not exceed +85C ambient for reliable 24/7 operation.
The 256-ball PBGA requires a 4-layer or 6-layer PCB with microvia technology or 0.5 mm-pitch via-in-pad for the BGA fanout. Per NXP layout guidelines, allocate continuous ground planes on layers 2 and 5, and place SDRAM and flash as close to the address/data bus balls as possible to minimize bus skew. Decoupling requires at least 10x 100 nF ceramic capacitors plus 4x 10 uF bulk caps within 5 mm of the VDD/VCC balls, per the MPC875 hardware reference manual.
Common pitfalls when designing with the MPC875ZT133: (1) Do not exceed 1.9 V on the core supply rail or the silicon will be damaged. (2) The part is EOL - do not start new production designs without sourcing a current-production replacement like the MPC8272 PowerQUICC II successor. (3) Boot configuration word values must match the BSDAT and BCFG pins at reset - check the reference manual's reset configuration section. (4) The CPM baud-rate generator requires careful divisor calculation for non-standard clock inputs.
Compliance Information
Compliance status not specified in provided data; RoHS/REACH should be verified against the NXP product page or contact Rochester Electronics for legacy EOL compliance documentation. AEC-Q100 is not applicable as this is a commercial/industrial MPU.
