MT25QL128ABB8ESF-0AUT - 128Mb SPI NOR Flash 133MHz | Micron
MPN: MT25QL128ABB8ESF-0AUT ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $5.5292 | $5.53 |
| 10 | $5.28 | $52.80 |
| 100 | $4.85 | $485.00 |
| 500 | $4.4 | $2,200.00 |
| 1,000 | $4.02 | $4,020.00 |
Drop-in alternatives for MT25QL128ABB8ESF-0AUT — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
MT25QL128ABB8E12-0AUT
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$3.62 / Unit
View Datasheet →MT25QL256ABA8E12-0AUT
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$12.5 / Unit
View Datasheet →MT25QL512ABB8E12-0AUT
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$10.55 / Unit
View Datasheet →MT25QL01GBBB8E12-0AUT
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$4.65 / Unit
View Datasheet →MT25QL02GCBB8E12-0AUT
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$7.65 / Unit
View Datasheet →MT25QU512ABB8E12-0AUT
✅ Drop-In ⚠️ 参数待验证✓ In Stock
Contact for price
View Datasheet →MT25QL128ABB8ESF-0AUT Maximum Ratings & Electrical Characteristics
| Memory Type | NOR Flash - Serial (SPI/Dual/Quad SPI) |
| Density | 128 Mbit (16 MB) |
| Supply Voltage (VCC) | 3 V (2.7 V to 3.6 V) |
| Maximum Clock Frequency | 133 MHz |
| Interface | SPI - Quad I/O (SPI, Dual SPI, Quad SPI) |
| Package | 16-SOP2 (16-pin SOIC) |
| Operating Temperature | -40C to +125C |
| Grade | Automotive (AEC-Q100) |
| FBGA Die Code | RW311 |
| Organization | 128M x 1 / 64M x 2 / 32M x 4 bit |
| Mounting Type | Surface Mount |
| Product Longevity Program | No |
| Protocol Family | MT25Q (ESF standard SPI instruction set) |
| Addressing | 3-byte and 4-byte address modes |
| Access Time | 6 ns |
| RoHS Status | Compliant |
| Marking Code | RW311 |
MT25QL128ABB8ESF-0AUT Pin Configuration
| Pin 1 | S# — Chip select (active low) |
| Pin 2 | DQ1 (SO) — Serial data output / DQ1 in Dual/Quad SPI |
| Pin 3 | W#/VPP (DQ2) — Write protect / VPP / DQ2 in Quad SPI |
| Pin 4 | VSS — Ground |
| Pin 5 | DQ0 (SI) — Serial data input / DQ0 in Dual/Quad SPI |
| Pin 6 | C — Serial clock |
| Pin 7 | HOLD#/DQ3 — Hold / DQ3 in Quad SPI |
| Pin 8 | VCC — Power supply (2.7 V to 3.6 V) |
| Pin 9 | NC — Not connected (per datasheet) |
| Pin 10 | NC — Not connected (per datasheet) |
| Pin 11 | NC — Not connected (per datasheet) |
| Pin 12 | NC — Not connected (per datasheet) |
| Pin 13 | NC — Not connected (per datasheet) |
| Pin 14 | NC — Not connected (per datasheet) |
| Pin 15 | NC — Not connected (per datasheet) |
| Pin 16 | NC — Not connected (per datasheet) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
MT25QL128ABB8ESF-0AUT is suitable for 6 applications: Automotive ECU Boot Memory, FPGA Configuration Storage, Industrial PLC and Automation Firmware, Networking Equipment Code Storage, Set-Top Box and Graphics Code Shadowing, Battery-Powered IoT and Telematics Devices.
Automotive ECU Boot Memory
The MT25QL128ABB8ESF-0AUT is qualified to AEC-Q100 and rated -40C to +125C, matching the under-hood and chassis requirements of engine control units, body controllers, and gateway modules. Its 133 MHz Quad SPI read delivers the boot throughput that modern AUTOSAR-class MCUs need for fast startup, and the 16MB density comfortably holds a bootloader plus application image and calibration data with margin for OTA update dual-banking. Because Micron's ESF instruction set follows the standard SPI command map, mainstream automotive MCU boot ROMs and external boot loaders operate it without custom drivers. Designers typically clock the device at 80-133 MHz in Quad I/O XiP mode, cutting boot time by more than half versus single-bit SPI reads at 50 MHz.
Recommended
FPGA Configuration Storage
Serial NOR Flash is the dominant configuration store for FPGAs, and the MT25QL128ABB8ESF-0AUT's 128Mb density plus 133 MHz Quad SPI read minimizes configuration time after power-up. For Microchip (Microsemi) RTAX and PolarFire-class designs, the ESF standard SPI instruction set ensures the FPGA configuration controller can issue conventional 0x03 fast-read and 0xEB Quad I/O fast-read commands directly. The 16-SOP2 footprint is widely used on HiRel and space-adjacent boards (see the RTAX and A3P parts listed on this site) because it is hand-assemblable and wave-compatible. A 16MB device covers bitstreams for mid-range devices; for larger fabrics, footprint-compatible MT25QL512/01GB parts enable upgrade without PCB change.
Recommended
Industrial PLC and Automation Firmware
Programmable logic controllers and factory automation nodes require firmware storage that survives vibration, wide temperature swings, and field OTA updates. The MT25QL128ABB8ESF-0AUT's -40C to +125C range and surface-mount 16-SOP2 package meet these mechanical and thermal demands, while 16MB accommodates a bootloader, RTOS image, application code, and log storage on a single device. Quad SPI XiP execution at 133 MHz keeps interrupt-latency-critical control loops deterministic, since the CPU reads code in place instead of first copying to RAM. The device's volatile and non-volatile configuration registers let designers latch Quad mode at production, so the memory always powers up in 4-bit mode regardless of stray bus activity during brownout events.
Recommended
Networking Equipment Code Storage
Routers, switches, and small-cell basestations store bootloaders, device trees, and golden firmware images in serial NOR because of its fast random access and in-place execution. The MT25QL128ABB8ESF-0AUT provides 133 MHz Quad SPI throughput, which cuts U-Boot load time significantly compared with 50-80 MHz legacy NOR, and 16MB is the sweet spot for dual golden-image schemes with redundancy. The 3-byte/4-byte address flexibility matters here: 4-byte addressing is standard practice in networking stacks and is supported natively. The automotive AEC-Q100 grade of the -0AUT suffix also gives telecom OEMs a reliability margin beyond commercial-grade SPI NOR at similar cost.
Recommended
Set-Top Box and Graphics Code Shadowing
Set-top boxes, smart displays, and graphics SoCs boot from serial NOR and then shadow code into DDR for execution. The MT25QL128ABB8ESF-0AUT's 133 MHz Quad SPI (with DDR support on the MT25Q platform) supplies the burst read bandwidth that keeps power-on-to-logo times short, while 16MB holds the boot ROM chain, device tree, and boot loader entirely. Micron's MT25Q die (RW311) also supports the extended I/O instruction set in sibling parts, giving firmware teams protocol headroom across product variants using the same PCB. In consumer AV designs, the wide -40C to +125C automotive rating of this specific order code eliminates a separate commercial BOM line for harsh-environment AV installations.
Recommended
Battery-Powered IoT and Telematics Devices
Cellular IoT modules, trackers, and telematics units need non-volatile firmware plus OTA update capability on a tight power budget. The MT25QL128ABB8ESF-0AUT operates from a 3.0V rail (2.7V-3.6V) that aligns with Li-SOCl2 and boost-regulated Li-ion supplies, and its deep power-down and sector-protect features reduce standby drain between wake cycles. 16MB supports a main image plus a full OTA staging image, a hard requirement for cellular firmware updates that must survive power loss mid-flash. Where the system rail is 1.8V, the footprint-compatible MT25QU512ABB8E12 (same 16-SOP2 outline) swaps in without PCB respin, trading density for voltage domain match.
Recommended
Recommended Products Summary
Engineering reference data for MT25QL128ABB8ESF-0AUT — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | MT25QL128ABB8E12-0AUT | MT25QL256ABA8E12-0AUT | MT25QL512ABB8E12-0AUT | MT25QU512ABB8E12-0AUT |
|---|---|---|---|---|---|
| Package | 16-SOP2 (16-pin SOIC) | 16-SOP2 - same | 16-SOP2 - same | 16-SOP2 - same | 16-SOP2 - same |
| Brand | Micron Technology | Micron Technology | Micron Technology | Micron Technology | Micron Technology |
| Density | 128 Mb (16 MB) | 128 Mb (16 MB) | 256 Mb (32 MB) | 512 Mb (64 MB) | 512 Mb (64 MB) |
| Supply Voltage | 3 V (2.7 V - 3.6 V) | 3 V | 3 V | 3 V | 1.8 V |
| Max Clock Frequency | 133 MHz | 133 MHz | 133 MHz | 133 MHz | 133 MHz |
| Protocol | ESF (standard SPI/Dual/Quad SPI) | XIO (extended I/O) | XIO (extended I/O) | XIO (extended I/O) | XIO (extended I/O) |
| Operating Temperature | -40C to +125C (AUT) | -40C to +125C | -40C to +105C | -40C to +85C | -40C to +85C |
| Addressing | 3-byte / 4-byte | 3-byte / 4-byte | 4-byte required above 16MB | 4-byte required | 4-byte required |
| Price (qty 1, as of 2026-09-02) | $5.53 (LCSC) | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
Key Differentiators
- Standard SPI instruction set (ESF) for maximum controller compatibility (vs MT25QL128ABB8E12-0AUT)
- Automotive temperature grade in commodity package (vs MT25QL512ABB8E12-0AUT)
- 16MB density minimizes cost for dual-image OTA designs (vs MT25QL256ABA8E12-0AUT)
Design Notes
At 133 MHz Quad SPI, treat the SPI bus as a moderate-speed transmission line: keep trace length under 15 cm, match the clock to data skew within ~1 ns, and place 100 nF ceramic decoupling within 3 mm of the VCC pin plus a bulk 4.7 uF per supply group. The 16-SOP2 package's VCC pin (pin 8) and VSS (pin 4) are at opposite corners - route a low-inductance ground pour under the device to close the return loop and reduce simultaneous-switching noise on DQ0-DQ3.
The ESF suffix matters at the protocol layer: the MT25QL128ABB8ESF-0AUT uses the standard SPI instruction set, while the pin-identical E12 parts use Micron's XIO feature set. A bootloader written for one will not execute correctly on the other even though timing and pinout match. Similarly, densities above 128Mb require 4-byte address commands; do not assume the ESF 3-byte addressing carries over when swapping in a 256Mb+ footprint-compatible part for a firmware upgrade path.
Hold VCC within 2.7 V to 3.6 V and observe the datasheet power-up ramp requirement before asserting S# low - most NOR Flash failures in the field trace to brownout conditions where VCC dips below minimum while the controller continues clocking. Add a supervisor reset for the host controller if the supply is shared with an inductive load (motors, relays). Estimated: at 133 MHz Quad SPI read, ICC is in the tens of milliamps range per the datasheet; budget the 3V rail accordingly in battery-powered designs.
Compliance Information
RoHS/lead-free per DigiKey, Mouser, Arrow, and LCSC distributor listings. AEC-Q100 per Arrow product data for the -0AUT automotive grade. Product Longevity Program: No (per Micron catalog data via digchip).
