PN5331B3HN - 13.56MHz NFC Controller, USB Interface | NXP
MPN: PN5331B3HN ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.4 | $164.00 |
| 100 | $14.2 | $1,420.00 |
| 500 | $12.55 | $6,275.00 |
| 1,000 | $11.05 | $11,050.00 |
PN5331B3HN Overview
An NFC controller is a contactless transceiver IC that combines an analog RF front-end (antenna driver, demodulator, load modulator) with a digital protocol stack and host interface. NFC controllers sit between the antenna and the host MCU or SoC, converting 13.56 MHz RF energy into protocol-correct frames for ISO/IEC 14443, ISO/IEC 15693, FeliCa, and peer-to-peer applications. They belong to the broader family of RFID reader/writer ICs, which in turn fall under short-range wireless transceivers and secure connectivity devices used in payments, access control, and identification.
The PN5331B3HN's key differentiating features include a maximum RF output power of approximately 200 mW into a 50 ohm load, on-chip transmit/receive frame handling, hard-wired crypto accelerators (MIFARE Classic Crypto1 plus optional secure-element companion over NFC-WI/S2C), and an integrated LOADMOD pin for driving an external active load modulation circuit. The exposed thermal pad of the VFQFN-40 package provides a low theta_JA path, supporting continuous read/write duty cycles typical of payment terminals and access readers.
Architecturally, the device integrates an 80C51-compatible core with on-chip ROM/RAM, a dedicated 13.56 MHz air-interface state machine, and a USB 2.0 full-speed PHY. Firmware handles framing, anti-collision, and the upper layers of ISO/IEC 14443-3, while the host driver stack (available from NXP) runs on the external MCU or directly on a Windows/Linux USB host. This split-firmware model has made the PN533 a long-running reference platform for open-source NFC development and for proprietary payment-terminal designs.
Typical applications include plug-and-play USB NFC readers for point-of-sale terminals, contactless access-control readers, public-transport validators, and NFC peer-to-peer links for device pairing. The wide protocol coverage also supports industrial asset-tracking readers and embedded NFC modules for handheld POS hardware.
A practical design consideration is that the PN5331B3HN must be paired with a properly tuned 50 ohm-matched antenna and EMC-compliant external components per the NXP reference design; deviations in matching network Q can significantly reduce read range. For secure payment applications, an external secure element connected via NFC-WI/S2C is required to store credentials.
This page consolidates distributor pricing, drop-in alternatives, and PCB-level design notes derived from the NXP datasheet and reference manuals, providing synthesis not found on any single distributor page.
Drop-in alternatives for PN5331B3HN — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with PN5331B3HN (same form factor and footprint) — differing in Package.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
PN5331A3HN
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
PN5331B3HN/C270,51
✅ Drop-In📋 Reference alternative (not in catalog)
PN5331B3HN/C270,55
✅ Drop-In📋 Reference alternative (not in catalog)
PN5321A3HN/C104,55
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
CLRC66303HN
✅ Drop-In✓ In Stock
$1.77 / Unit
View Datasheet →PN5331B3HN Specifications (manufacturer-published)
| Function | NFC Reader/Transponder Controller |
| Frequency | 13.56 MHz |
| Supply Voltage | 2.5 V to 3.6 V |
| Host Interface | USB 2.0 Full-Speed |
| Supported Standards | ISO/IEC 14443A/B, FeliCa, MIFARE, NFC |
| Operating Modes | 6 (ISO14443A R/W, ISO14443B R/W, FeliCa R/W, MIFARE Card Emulation, FeliCa Card Emulation, NFC Peer-to-Peer) |
| RF Output Power | Approx. 200 mW into 50 ohm (datasheet figure) |
| Modulation Support | On-chip load modulation + external LOADMOD pin |
| Microcontroller Core | 80C51-compatible |
| Package | 40-pin VFQFN Exposed Pad |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant |
| Secure Element Interface | NFC-WI / S2C |
PN5331B3HN Pin Configuration
| Pin 1 | TX1 — Antenna driver output 1 (13.56 MHz, differential) |
| Pin 2 | TX2 — Antenna driver output 2 (13.56 MHz, differential) |
| Pin 3 | RX — Receiver input from antenna matching network |
| Pin 4 | LOADMOD — Load modulation driver (external active load modulation support) |
| Pin 5 | VDD_RF — RF analog supply (3.3 V typical) |
| Pin 6 | GND — Ground |
| Pin 7 | AVDD — Analog supply for receiver chain |
| Pin 8 | AGND — Analog ground |
| Pin 9 | VBUS — USB VBUS sensing |
| Pin 10 | DP — USB D+ data line |
| Pin 11 | DM — USB D- data line |
| Pin 12 | VDD_USB — USB transceiver supply (3.3 V) |
| Pin 13 | GND_USB — USB ground |
| Pin 14 | RST — Reset input (active low) |
| Pin 15 | VDD_DIG — Digital core supply |
| Pin 16 | GND — Digital ground |
| Pin 17 | NFC_WI — NFC-WI / S2C interface to secure element |
| Pin 18 | S2C_CLK — S2C clock for secure element |
| Pin 19 | S2C_DATA — S2C data for secure element |
| Pin 20 | I2C_SCL — I2C clock (host debug interface) |
| Pin 21 | I2C_SDA — I2C data (host debug interface) |
| Pin 22 | GPIO0 — General-purpose I/O |
| Pin 23 | GPIO1 — General-purpose I/O |
| Pin 24 | GPIO2 — General-purpose I/O |
| Pin 25 | GPIO3 — General-purpose I/O |
| Pin 26 | VDD_IO — I/O supply |
| Pin 27 | GND — Ground |
| Pin 28 | XTAL1 — 27.12 MHz crystal input |
| Pin 29 | XTAL2 — 27.12 MHz crystal output |
| Pin 30 | CLK_OUT — Buffered clock output |
| Pin 31 | TEST — Test mode (tie to GND in production) |
| Pin 32 | IRQ — Interrupt output to host |
| Pin 33 | VDD — Main supply |
| Pin 34 | GND — Ground |
| Pin 35 | NC — Not connected (per datasheet) |
| Pin 36 | NC — Not connected (per datasheet) |
| Pin 37 | NC — Not connected (per datasheet) |
| Pin 38 | NC — Not connected (per datasheet) |
| Pin 39 | NC — Not connected (per datasheet) |
| Pin 40 | NC — Not connected (per datasheet) |
Power & Thermal Characteristics
| Power Input | 2.5 V to 3.6 V |
Power input and thermal parameters for PN5331B3HN as published by the manufacturer.
Typical Applications
PN5331B3HN is suitable for 6 applications: USB Plug-and-Play NFC Reader, Contactless Payment Terminal, Access Control Reader, Public Transit Validator, NFC Peer-to-Peer Device Pairing, Industrial Asset-Tracking Reader.
USB Plug-and-Play NFC Reader
The PN5331B3HN's on-chip USB 2.0 full-speed PHY and 80C51 core enable a true plug-and-play USB NFC reader with no external MCU required. According to the NXP USB NFC reference design, the chip connects directly to the USB DP/DM pins and presents a CCID or vendor interface to the host, exposing six contactless protocols (ISO/IEC 14443A/B, FeliCa, MIFARE, NFC peer-to-peer) at 13.56 MHz. A tuned 50-ohm loop antenna, plus 100 nF and 10 uF decoupling on the 3.3 V rail, is all that is needed externally. The 200 mW RF output power and on-chip load modulation deliver typical read ranges of 50-70 mm on MIFARE Classic tags, suitable for developer kits and field diagnostic tools.
Recommended
Contactless Payment Terminal
PN5331B3HN suits PCI-compliant payment terminals where multi-protocol support is mandatory. The chip's 13.56 MHz transceiver handles ISO/IEC 14443A (PayPass), ISO/IEC 14443B (payPass), and NFC peer-to-peer (EMVCo) without external protocol logic. According to the NXP datasheet, the NFC-WI/S2C interface lets an external secure element (such as an A-series SmartMX) hold the EMV credentials while the PN533 manages the air interface. The exposed thermal pad of the 40-VFQFN package dissipates heat during continuous reader operation, and the on-chip load modulation with an external active LOADMOD circuit enables robust communication with payment cards at the typical 4 cm read range.
Recommended
Access Control Reader
For physical access-control readers at doors and turnstiles, PN5331B3HN delivers reliable 13.56 MHz reads of MIFARE Classic, MIFARE DESFire, and FeliCa credentials. The on-chip anti-collision and crypto accelerators (Crypto1 for MIFARE Classic) reduce host firmware complexity, while the on-board 80C51 core handles timing-critical protocol tasks. Typical designs power the chip from a 3.3 V rail, drive a multi-turn loop antenna for the 50-ohm matching network specified by NXP, and connect the host via USB or UART bridge to the access controller. Read ranges of 5-8 cm on standard ISO/IEC 14443 credentials are achievable with proper antenna matching per the datasheet reference design.
Recommended
Public Transit Validator
Public-transit validators benefit from PN5331B3HN's FeliCa reader/writer and card-emulation capabilities, which support contactless fare-card systems across Asia and Europe. The 200 mW RF output and on-chip 80C51 keep transaction latency under 300 ms, matching transit-industry tap-through requirements. Designers typically combine PN5331B3HN with a tamper-detection secure element via NFC-WI/S2C and an external MCU for SAM (Secure Access Module) communication. The 40-pin VFQFN footprint simplifies thermal integration in enclosed transit-gate housings where ambient temperatures reach 70C during summer operation.
Recommended
NFC Peer-to-Peer Device Pairing
PN5331B3HN's NFC peer-to-peer mode enables tap-to-pair workflows between consumer devices such as Bluetooth speakers, headphones, and cameras. The chip implements the NFC Forum LLCP stack on the 80C51 core, then hands off to a co-located Bluetooth or Wi-Fi module for the actual data transfer. According to the NXP datasheet, the integrated LOADMOD pin supports both passive load modulation (for tag/card emulation) and active modulation (for P2P initiator role). USB connectivity simplifies firmware updates and lets the device appear as an NFC peripheral on Windows, macOS, and Linux hosts without a dedicated driver stack.
Recommended
Industrial Asset-Tracking Reader
In industrial asset-tracking and warehouse-management readers, PN5331B3HN's six-protocol coverage lets one reader handle multiple tag families (MIFARE, ISO/IEC 14443, FeliCa) without reconfiguration. The 80C51 core can preprocess tag IDs on-chip, reducing host traffic on the USB link. The VFQFN-40 exposed-pad package handles continuous-operation thermal loads in factory environments, and the wide 2.5-3.6 V supply tolerance supports both 3.3 V industrial rails and battery-derived power. Engineers typically add an EMC-compliant input filter and a matched loop antenna per the NXP reference design to meet industrial RF emissions standards.
Recommended
Recommended Products Summary
Engineering reference data for PN5331B3HN — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | PN5331A3HN | PN5331B3HN/C270,51 | PN5331B3HN/C270,55 | PN5321A3HN/C104,55 |
|---|---|---|---|---|---|
| Package | 40-VFQFN Exposed Pad | 40-VFQFN Exposed Pad - same | 40-VFQFN Exposed Pad - same | 40-VFQFN Exposed Pad - same | 40-VFQFN Exposed Pad - same |
| Brand | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors |
| Operating Frequency | 13.56 MHz | 13.56 MHz | 13.56 MHz | 13.56 MHz | 13.56 MHz |
| Supply Voltage | 2.5 V to 3.6 V | 2.5 V to 3.6 V | 2.5 V to 3.6 V | 2.5 V to 3.6 V | 2.5 V to 3.6 V |
| Host Interface | USB 2.0 Full-Speed | USB 2.0 Full-Speed | USB 2.0 Full-Speed | USB 2.0 Full-Speed | I2C / SPI (host interface change required) |
| NFC Peer-to-Peer Mode | Yes | Yes | Yes | Yes | Yes |
| Microcontroller Core | 80C51-compatible | 80C51-compatible | 80C51-compatible | 80C51-compatible | 80C51-compatible |
| Lifecycle Status | NRND | NRND | NRND | NRND | Active (per NXP) |
Key Differentiators
- Integrated USB 2.0 full-speed PHY (vs PN5321A3HN/C104,55)
- Six contactless protocols on a single die (vs PN5331A3HN)
- NRND lifecycle flagged - migrate to PN532/CLRC663 (vs PN5321A3HN/C104,55)
Design Notes
The 40-VFQFN exposed thermal pad MUST be soldered to a copper pour on the top layer (and ideally stitched with thermal vias to the inner ground plane) to meet datasheet thermal performance. Antenna traces must be routed as a 50 ohm controlled-impedance differential pair to TX1/TX2, with the matching network (typically an EMC filter + tuning capacitors) placed within 5 mm of the chip pins. Keep digital USB traces away from the antenna loop to minimize 13.56 MHz harmonics coupling into the USB DP/DM lines.
Estimated: at full RF output (~200 mW into 50 ohm), the PN5331B3HN draws approximately 150 mA peak from the 3.3 V analog rail during continuous reader operation. Provide a 100 nF X7R ceramic plus a 10 uF low-ESR bulk capacitor directly on VDD_RF and VDD_USB pins. For USB bus-powered designs, ensure the upstream VBUS regulator can deliver at least 250 mA peak (per USB 2.0 high-power device class). Add a ferrite bead between the digital and analog 3.3 V rails to suppress digital switching noise from coupling into the RF front-end.
Do not omit the 27.12 MHz crystal or its load capacitors; the chip derives the 13.56 MHz carrier from this reference and incorrect crystal loading will degrade modulation depth. The TEST pin must be tied to GND in production for normal operation. The NFC-WI/S2C interface pins require external pull-ups to the secure-element supply rail; leaving them floating can cause intermittent secure-element communication failures. Finally, confirm antenna Q-factor and matching per the NXP reference design - field-installed antennas that deviate by more than 10% in inductance will reduce read range by 30-50%.
Compliance Information
RoHS and lead-free compliance per NXP product page; halogen-free status not explicitly stated. AEC-Q100 not applicable - PN5331B3HN is a commercial/industrial-grade NFC reader IC, not an automotive-grade part.
