PN7642 - NFC Reader IC with Cortex-M33 MCU & Security | NXP
MPN: PN7642 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $5.8 | $5.80 |
| 10 | $5.22 | $52.20 |
| 100 | $4.64 | $464.00 |
| 500 | $4.06 | $2,030.00 |
| 1,000 | $3.48 | $3,480.00 |
PN7642 Overview
An NFC reader controller is a single-chip integration of an RF analog front end (for 13.56 MHz contactless communication), protocol firmware, and a host-processing MCU. Within the system hierarchy, it belongs to the RF & Wireless > NFC/RFID reader family: antenna driver -> NFC frontend -> NFC controller with MCU (PN7462, PN7642). By merging reader, MCU, and secure element, the PN7642 replaces the need for an extra discrete MCU and a dedicated Secure Element in the bill of materials, reducing board area and BOM cost in payment and access-control designs.
Key features include the integrated Common Criteria EAL6+ certified secure element, EMVCo certification for contactless payments, support for ISO 14443 (Type A and Type B) and NFC Forum protocols, and the Arm Cortex-M33 core with 180 kB of user-programmable flash. GPIO resources include multi-function pins such as GPIO2 (PWM2 capability) and GPIO3 (PWM3 capability); when ULPCD (Ultra-Low-Power Card Detection) is used, GPIO3 must be dedicated to aborting the ULPCD function and cannot be allocated to other roles.
Technically, the PN7642 pairs a high-performance NFC frontend with a customizable MCU subsystem, enabling customer firmware to implement application logic, key management, and cryptographic operations on-chip. The security toolbox addresses secure key storage, a primary requirement for payment terminals and secure access readers, and the part is supplied in a compact BGA package suitable for space-constrained embedded designs.
Typical applications include EMVCo contactless payment terminals, secure access-control and identity readers, and NFC-enabled IoT devices that require both contactless connectivity and embedded security without external components.
Design consideration: firmware architecture must account for pin multiplexing constraints such as GPIO3 contention with ULPCD, and designers should consult NXP design-in documents beyond the product data sheet, since detailed design-in information is distributed separately by NXP.
This page synthesizes verified distributor pricing, drop-in alternative analysis, and practical design notes not found in the manufacturer datasheet.
Drop-in alternatives for PN7642 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with PN7642 (same form factor and footprint) — differing in Package, Function, RoHS Status, Mounting Type, Host Interfaces.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
PN7642EV-C100K
✅ Drop-In✓ In Stock
$8.89 / Unit
View Datasheet →PN7642EV-C101Y
✅ Drop-In✓ In Stock
$10.18 / Unit
View Datasheet →PN7642EV
✅ Drop-In✓ In Stock
$10.18 / Unit
View Datasheet →PN7642EV/C101K
✅ Drop-In📋 Reference alternative (not in catalog)
PN7220
✅ Drop-In✓ In Stock
$2.75 / Unit
View Datasheet →PN7642 Specifications (manufacturer-published)
| Product Type | NFC open controller (reader + MCU + secure element) |
| Core | Arm Cortex-M33 |
| Programmable Flash | 180 kB |
| RF Frequency | 13.56 MHz (HF, NFC) |
| Supported NFC Protocols | ISO 14443 Type A and Type B; NFC Forum |
| Security Certification | Common Criteria EAL6+ |
| Payment Certification | EMVCo compliant |
| Host Interface | SPI (per PN76 family quick start guide) |
| Package | BGA (PN7642EV orderable variants) |
| Mounting Type | Surface Mount |
| GPIO | Multi-function; GPIO2 (PWM2), GPIO3 (PWM3) |
| ULPCD Support | Yes; GPIO3 must be dedicated to ULPCD abort when used |
| RoHS Status | Compliant (per NXP product page) |
PN7642 Interfaces & Connectors
PN7642 exposes the following interfaces and connectors as published by the manufacturer: GPIO. Expansion header pinout, connector pin numbering, and electrical limits are defined in the manufacturer documentation.
| GPIO | Multi-function; GPIO2 (PWM2), GPIO3 (PWM3) |
Refer to the manufacturer documentation for the full expansion header pinout and connector pin numbering.
Typical Applications
PN7642 is suitable for 6 applications: EMVCo Contactless Payment Terminal, Secure Access Control Reader, NFC-Enabled IoT Provisioning and Pairing, Identity and eDocument Verification, Public Transport and Transit Ticketing, Industrial NFC Configuration and Diagnostics.
EMVCo Contactless Payment Terminal
The PN7642's integrated EMVCo certification and EAL6+ secure element make it a primary candidate for contactless point-of-sale terminals where certification time is a critical path. With 180 kB of user-programmable flash on the Cortex-M33 core, terminal firmware can host payment kernels, key management, and PCI-relevant cryptographic routines without an external MCU. Designers place the PN7642 between the 13.56 MHz antenna matching network and the host processor over SPI, while the on-chip secure element holds payment credentials. Compared with multi-chip solutions that pair a discrete NFC frontend with an external secure element, the PN7642 cuts PCB footprint by roughly 30-40 percent and accelerates lab re-certification cycles.
Recommended
Secure Access Control Reader
Physical access readers, electronic identity terminals, and secure door locks benefit from the PN7642's combination of NFC Forum and ISO 14443 Type A/B support together with EAL6+ key storage. The 180 kB flash supports on-reader authentication logic, while the integrated secure element protects credentials against physical tamper. Antenna tuning is simplified by the integrated frontend, eliminating the analog design burden of discrete NXP CLRC663 plus MCU solutions. Designers typically pair the PN7642 with a host MCU over SPI for upstream connectivity (Ethernet, RS-485, or wireless), while the secure element retains all cryptographic material locally.
Recommended
NFC-Enabled IoT Provisioning and Pairing
IoT devices that use NFC for out-of-band Wi-Fi or Bluetooth pairing benefit from the PN7642's combination of reader mode, peer-to-peer, and integrated MCU. With 180 kB of flash, the on-chip Cortex-M33 can run provisioning flows locally, removing the need for a separate wireless MCU just to handle NFC handshakes. The PN7642's ULPCD mode, with GPIO3 dedicated to abort, enables card-detection at very low standby currents for battery-powered devices. Compared with using a discrete NFC frontend plus a host processor, the integrated solution simplifies firmware architecture and reduces overall BOM cost.
Recommended
Identity and eDocument Verification
ePassport readers, eID inspection terminals, and document verification kiosks leverage the PN7642's ISO 14443 Type A/B and NFC Forum stack together with EAL6+ secure element to meet high-assurance government requirements. The integrated secure element can store inspection keys and perform mutual authentication, while the 180 kB flash hosts extended APDU protocols. Antenna matching is easier than with discrete frontends, which is critical for the wider read range often required at border-control kiosks. Designers using the PN7642 for eDocuments should consult NXP's PN76 family evaluation board quick start guide (Section 3.1.4.1) for host-interface selection.
Recommended
Public Transport and Transit Ticketing
Transit readers, validators, and contactless ticket gates use the PN7642 to read ISO 14443 cards and NFC Forum devices in high-throughput environments. The integrated frontend supports fast transaction times needed for tap-and-go flows, while the EAL6+ secure element protects operator keys. ULPCD allows the reader to enter very low-power standby between user taps, important for battery-backed validators at bus stops or station entrances. Compared with discrete CLRC663-plus-MCU designs, the PN7642 reduces component count and simplifies EMI certification for embedded systems such as transit terminals.
Recommended
Industrial NFC Configuration and Diagnostics
Industrial equipment - PLCs, motor drives, sensor gateways - uses NFC tap-to-configure interfaces that the PN7642 enables without adding a full MCU. The on-chip Cortex-M33 with 180 kB flash hosts the configuration protocol, and the EAL6+ secure element can protect factory calibration data and authentication keys. Industrial designers benefit from the wide GPIO set and PWM-capable GPIO2/GPIO3 for status LEDs, while ULPCD keeps standby power low on battery-backed sensor nodes. Compared with discrete NXP PN5180A0HN designs, the PN7642 brings a modern Cortex-M33 core and stronger security certification to the same application.
Recommended
Recommended Products Summary
Engineering reference data for PN7642 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | PN7642EV-C100K | PN7642EV-C101Y | PN7642EV | PN7642EV/C101K | PN7220 |
|---|---|---|---|---|---|---|
| Brand | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors |
| Package | BGA (PN7642EV) | BGA (PN7642EV) - same | BGA (PN7642EV) - same | BGA (PN7642EV) - same | BGA (PN7642EV) - same | BGA - same platform |
| Core | Arm Cortex-M33 | Arm Cortex-M33 | Arm Cortex-M33 | Arm Cortex-M33 | Arm Cortex-M33 | Arm Cortex-M33 (PN76 family) |
| NFC Protocols | ISO 14443 A/B, NFC Forum | ISO 14443 A/B, NFC Forum | ISO 14443 A/B, NFC Forum | ISO 14443 A/B, NFC Forum | ISO 14443 A/B, NFC Forum | ISO 14443 A/B, NFC Forum |
| Host Interface | SPI (per PN76 quick start guide) | SPI | SPI | SPI | SPI | SPI (PN76 family) |
| Lifecycle Status | Active | Active | Active | Active | Active | Active |
Key Differentiators
- Integrated EAL6+ secure element on-chip (vs CLRC66303HN)
- Arm Cortex-M33 with 180 kB flash on-chip (vs PN5180A0HN/C4)
- EMVCo certified platform (vs ST25R3920B)
- Forward migration path to PN7220 (vs PN7642EV legacy variants)
Design Notes
GPIO3 is shared between PWM3 and the ULPCD abort function. When ULPCD is enabled, GPIO3 MUST be dedicated to aborting the ULPCD state machine and cannot be reused as a general-purpose I/O. Violating this constraint leads to undefined behavior in low-power card detection. Designers should review the datasheet pin table and pin-mux configuration early in the schematic phase, before committing the pinout.
The PN7642 integrates a 13.56 MHz NFC frontend that is sensitive to PCB layout. Place the antenna matching network as close to the PN7642 RF pins as possible, keep the matching components on the same layer, and maintain a solid ground plane beneath the RF traces. Decoupling capacitors should be placed within 2 mm of each VDD pin with a short, wide trace to ground. Reference NXP's PN76 family evaluation board quick start guide for the recommended host-interface and antenna layout patterns.
The PN7642 datasheet only describes electrical characteristics; detailed design-in information (host-interface configuration, firmware bring-up, evaluation board usage) is distributed in separate NXP documents and the PN76 family quick start guide. Designers should request the latest design-in package from NXP before starting PCB layout, since relying solely on the product data sheet will leave gaps in the host-interface configuration (per the PN76 evaluation board quick start guide, Section 3.1.4.1).
The PN7642 SPI host interface pins (Pin 10 CLK, Pin 12 MISO, Pin 14 MOSI, Pin 16 CS per the PN76 family evaluation board quick start guide) should be length-matched within approximately 5 mm and routed over a continuous ground plane to avoid reflections at high clock rates. Series termination near the source pin is recommended when total bus length exceeds 50 mm. Keep SPI traces away from the 13.56 MHz RF traces to avoid coupling into the digital signals.
Compliance Information
RoHS and REACH compliance per NXP product page. AEC-Q100 not applicable - PN7642 targets consumer payment and IoT, not automotive.
