STM32F767BIT6 - ARM Cortex-M7 MCU, 2MB Flash, 216MHz | STMicroelectronics
MPN: STM32F767BIT6 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.85 | $18.85 |
| 10 | $17.12 | $171.20 |
| 100 | $14.94 | $1,494.00 |
| 500 | $13.21 | $6,605.00 |
| 1,000 | $11.85 | $11,850.00 |
STM32F767BIT6 Overview
What is a Cortex-M7 MCU? An ARM Cortex-M7 microcontroller is a high-end 32-bit microcontroller core designed by Arm for deterministic real-time embedded systems. The Cortex-M7 belongs to the Cortex-M family and is positioned above Cortex-M4 by adding a double-precision FPU, single-precision floating-point pipeline, branch prediction, and tightly-coupled instruction/data caches. The STM32F7 line is part of ST's mainstream performance tier that also introduces MIPI-DSI display, USB Type-C / Power Delivery and a richer analog set over the F4 generation, making it suitable for industrial control, audio DSP, HMI graphics and motor-control loops.
Key features of the STM32F767BIT6 include: up to 18 timer channels, three 12-bit ADC converters (up to 2.4 MSPS each), two 12-bit DACs, a USB 2.0 OTG full-speed/high-speed PHY, two CAN 2.0B controllers, an SDIO/MMC interface, a Quad-SPI flash interface and an LCD-TFT controller. The Cryptography block accelerates AES-256, SHA-1/SHA-2 hashing, and true RNG, easing secure-boot and TLS link setups. The 208-LQFP footprint routes out 162 GPIO pins plus a wide parallel-interface bus, sufficient for SDRAM + TFT display + Ethernet + USB Type-C concurrently.
The architecture pairs a dual-issue FPU + DSP pipeline with ART Accelerator to minimise flash wait-states; combined with the 16 KB L1 cache, the device achieves 462 DMIPS at 216 MHz with deterministic interrupt latency of <30 ns typical. Cryptography hardware offloads AES, SHA-1/2 and RNG; this dramatically reduces CPU overhead in TLS handshakes compared to software-only implementations. Embedded SRAM is split into 384 KB DTCM + 128 KB SRAM + 4 KB backup SRAM, with the SDRAM controller extending external memory up to 32-bit wide for display or data buffers.
Typical applications are industrial HMI panels, motor drives and servo controllers, USB-C PD chargers and audio DSP platforms. The combination of TFT-LCD controller + DMA2D + SDRAM controller + USB high-speed on-chip PHY makes the F767 a single-chip candidate for 4.3-inch touchscreen displays with secure field updates.
When designing with this device the 1.7-3.6 V supply and an external 25 MHz HSE crystal (with optional LSE 32.768 kHz for RTC) must be provided. Decoupling follows ST AN4365 placement rules: 100 nF + 4.7 µF near each VDD/VSS pair, plus a dedicated 1 µF bulk for the USB OTG PHY rail. For SDRAM operation use layed-out matched length with VREF = VDD/2 and 50 Ω impedance; bypass VBAT with a 0.1 µF cap if no battery is fitted.
Drop-in alternatives for STM32F767BIT6 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with STM32F767BIT6 (same form factor and footprint) — differing in Package, Core, Operating Temperature, SRAM, Communication Interfaces.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
STM32F765BIT6
✅ Drop-In📋 Reference alternative (not in catalog)
STM32F769BIT6
✅ Drop-In✓ In Stock
$13.4 / Unit
View Datasheet →STM32F767BIT6 Maximum Ratings & Electrical Characteristics
| Core | ARM Cortex-M7 with FPU + DSP instructions |
| Maximum CPU Clock | 216 MHz |
| DMIPS | 462 DMIPS (2.14 DMIPS/MHz, Dhrystone 2.1) |
| Program Flash | 2 MB (single-bank, 32-bit fetch) |
| SRAM | 384 KB DTCM + 128 KB SRAM + 4 KB backup SRAM |
| L1 Cache | 16 KB I-cache + 16 KB D-cache |
| ART Accelerator | Yes (0-wait-state execution from Flash) |
| Operating Voltage | 1.7 V to 3.6 V |
| Package | 208-LQFP (28x28 mm), 0.5 mm pitch |
| I/O Pins (max) | 162 GPIOs |
| ADC | 3 x 12-bit, up to 2.4 MSPS each |
| DAC | 2 x 12-bit |
| Timers | up to 18 channels incl. 32-bit, IC/OC, PWM |
| USB | USB 2.0 OTG FS + HS with integrated HS PHY |
| CAN | 2 x CAN 2.0B |
| Crypto / Hash | AES-256, SHA-1/2, TRNG (hardware) |
| External Memory Bus | SDRAM (up to 32-bit) + SRAM/PSRAM/NOR/NAND |
| Display Controller | LCD-TFT, up to 1024x768 + DMA2D |
| Octo-SPI / Quad-SPI | 1 x Octo-SPI / 1 x Quad-SPI |
| Operating Temperature | -40°C to +85°C (Grade 6) |
| Mounting Type | Surface Mount |
| MSL Level | 3 (per JEDEC J-STD-020) |
| RoHS Status | Compliant |
STM32F767BIT6 208-lqfp (28x28 mm), 0.5 mm pitch Pin Configuration Guide
Pin configuration for STM32F767BIT6 (208-lqfp (28x28 mm), 0.5 mm pitch package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for STM32F767BIT6.
Refer to the datasheet for full pin configuration.
Typical Applications
STM32F767BIT6 is suitable for 6 applications: Industrial HMI Touch Panels, Servo / BLDC Motor Control, USB Type-C PD Chargers, Audio DSP / Effects Processors, M2M / Industrial Ethernet Gateways, Medical Wearable Sensors.
Industrial HMI Touch Panels
Builds around the integrated LCD-TFT controller and DMA2D chrom-ART graphics engine plus 2 MB Flash for full-screen framebuffers in compressed form. Typical 4.3 to 5-inch LVDS/RGB TFT panels can be driven directly without external display driver. The 216 MHz Cortex-M7 with 16 KB L1 cache gives above 60 fps sprite animation for capacitive-touch UI shells.
Recommended
Servo / BLDC Motor Control
Provides 3 ADC pairs (each 12-bit / 2.4 MSPS), 18 timer channels and dedicated HRTIM for 3-phase PWM generation at the 216 MHz main clock. Field-oriented control loops run in <2 µs with deterministic interrupt latency below 30 ns from the FPU and DSP instruction set, allowing evaluation of sine-cosine field orientation in hardware time. The Cortex-M7's single-precision FPU eases Park/Clarke transforms without integer overflow issues.
Recommended
USB Type-C PD Chargers
Integrates USB 2.0 OTG Full-Speed + High-Speed with on-chip 480 Mbps PHY, eliminating the external HS PHY BOM on F4 designs. The Type-C Power Delivery protocol stack runs on the Cortex-M7 alongside CC pin detection and VBUS current sense using the integrated comparator - allows firmware to switch between PD-PPS and legacy BC1.2 charging modes. Hardware AES-256 fast-secures the MTP session without software round-off.
Recommended
Audio DSP / Effects Processors
Drives audio DSP effects, parametric EQ and S/PDIF streams at 24-bit/192 kHz using the DSP and FPU instructions across 1-2 channels simultaneously. The 512 KB SRAM holds local audio buffers with DMA from SAI/I2S peripherals, with zero-wait flash execution enabling on-the-fly effect chain swap during playback. Two 12-bit DACs and the SDIO controller allow stereo/multi-channel streaming with simple SD-card file playback.
Recommended
M2M / Industrial Ethernet Gateways
Routes the controller's 2x CAN 2.0B and USART to RS-485 interfaces while external DP83848 MAC-PHY converts to Ethernet; HTTP/MQTT stacks run on the 216 MHz Cortex-M7 with TLS using the AES-256 hardware block. The 4 KB backup SRAM maintains RTC + TLS session cache during a brown-out, and the 208-LQFP accommodates up to 162 GPIOs for sensor and indicator banks. ART Accelerator keeps the TLS handshake deterministically within 100 ms.
Recommended
Medical Wearable Sensors
Suitable for body-worn biosensor hubs thanks to 1.7-3.6 V supply range spanning a single Li-ion cell plus the integrated 12-bit ADC for ECG, PPG and SpO2 analogue front-ends. AES-256 encryption secures the patient's transmission stream for HIPAA-aligned gateways, and the BAT (backup-domain) keeps RTC live during deep-standby. Pin package keeps the BOM under 65 mm² versus discrete 8-bit designs for wearables.
Recommended
Recommended Products Summary
Engineering reference data for STM32F767BIT6 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | STM32F765BIT6 | STM32F769BIT6 |
|---|---|---|---|
| Brand | STMicroelectronics | STMicroelectronics | STMicroelectronics |
| Package | 208-LQFP (28x28 mm) | 208-LQFP - same | 208-LQFP - same |
| CPU Core | Cortex-M7 216 MHz | Cortex-M7 216 MHz | Cortex-M7 216 MHz |
| Flash Size | 2 MB | 2 MB | 2 MB |
| SRAM | 384 KB DTCM + 128 KB SRAM + 4 KB backup | 384 KB + 128 KB + 4 KB | 384 KB + 128 KB + 4 KB |
| MIPI-DSI Display | No | No | Yes (2-lane) |
| Crypto Block | AES-256 / SHA / TRNG | AES-256 / SHA / TRNG | AES-256 / SHA / TRNG + PKA |
| USB High-Speed PHY | Yes (integrated) | Yes (integrated) | Yes (integrated) |
| LCD-TFT Controller | Yes (8-bit RGB, up to 1024x768) | Yes (8-bit RGB) | Yes (RGB + MIPI-DSI) |
| Operating Temperature | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C |
Key Differentiators
- Mature Cortex-M7 platform with 2 MB Flash + 512 KB SRAM in 208-LQFP (vs STM32H743ZIT6)
- AES-256 + SHA + TRNG hardware crypto at zero CPU cost (vs STM32F746ZGT6)
- USB 2.0 High-Speed PHY and 480 Mbps PHY integrated (vs STM32F765IGT6 (LQFP-176))
Design Notes
Decouple each VDD/VSS pair with 100 nF + 4.7 µF ceramic placed within 3 mm of the IC pin; use a 1 µF bulk for the integrated USB HS PHY rail. The 1.7 V minimum supply requires a separate LDO if the rest of the board runs at 3.3 V but falls below 3.0 V occasionally; for proper reset behaviour ensure VDD is monotonic with rise time ≤ 10 ms. Typical VDD current at 216 MHz is ~70 mA during flash-accelerated code execution and rises to ~110 mA peak in DMA-driven LCD refresh loops.
Place the 25 MHz HSE crystal within 5 mm of the OSC pins with load capacitors sized to the crystal CL spec (typical 12-20 pF). Provide a clean analog ground island for the VREF+ ADC reference pin with a ferrite bead to digital GND. SDRAM traces must be length-matched within ±3 mm and 50 Ω impedance, with VREF = VDD/2 routed on its own shielded band for read/write margin.
Do not skip the BYPASS_REG pin decoupling - failure to do so causes unpredictable startup on the F767 family. When designing a 7-inch TFT, plan for DPRAM refresh and allocate one DMA2D channel exclusively for the chrom-ART engine to avoid UI tearing. The Octo-SPI/Quad-SPI bus uses Boot0/1 strapping resistors that are read at reset; mismatch between the BOOT0 pin state and firmware boot mode will leave the device in System Memory bootloader instead of main flash.
At 216 MHz execution the F767 typically dissipates under 0.5 W; a 208-LQFP with 1 oz copper pours keeps θJA below 30 °C/W. Heavy peripherals (e.g. full DMA2D 60 fps + USB HS driving) can push internal die up by another 30 °C - leave thermal budget margin by derating from 105 °C Tj to ensure headroom. Reference thermal performance from ST AN4553 'PCB design guidelines for thermal stress'.
For SDRAM at 108 MHz, the VREF decoupling is critical; place a 100 nF + 1 µF near the IC. USB DP / DM traces should be 90 Ω differential ±10%, with ESD protection (e.g. USBLC6-2SC6) within 3 mm of the connector. The MIPI-DSI is NOT present on the F767 - do not rely on F769-style DSI schematic drift if migrating firmware.
Compliance Information
RoHS and lead-free per ST ECOPACK Level 2 - dropped to Level 3 (-40 to +85 °C) for industrial grade. NOT AEC-Q100 qualified - select STM32F769AI line or STM32H7 automotive grade for vehicle use.
