STM32MP135AAC3 - 650MHz Arm Cortex-A7 MPU | STMicroelectronics
MPN: STM32MP135AAC3 β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $7.69 | $7.69 |
| 10 | $7.05 | $70.50 |
| 100 | $6.45 | $645.00 |
| 500 | $5.95 | $2,975.00 |
| 1,000 | $5.49 | $5,490.00 |
STM32MP135AAC3 Overview
An MPU (microprocessing unit) sits above an MCU in the embedded hierarchy: it runs rich operating systems such as Linux on a Cortex-A application core, offloading real-time tasks to companion Cortex-M devices or peripherals. The STM32MP1 series bridges this gap by combining an application processor with STM32-style peripherals, letting developers reuse STM32 ecosystem tools such as STM32CubeMX and STM32CubeProgrammer.
Key features include the single Cortex-A7 core with NEON and FPU, an LCD-TFT display interface, a parallel camera interface, 2x Gigabit-capable Ethernet MACs, 2x CAN FD controllers, 2x 12-bit ADCs, and 24 timers. External DRAM support follows the JEDEC LPDDR2 (JESD209-2E) and LPDDR3 (JESD209-3B) specifications over a 16-bit interface, with a programmable 8-bit or 16-bit data width, an advanced memory scheduler and three-class QoS support on reads.
The memory subsystem architecture includes an advanced SDRAM command generator and scheduler that maintains deterministic bandwidth under mixed traffic, which matters for display refresh plus network throughput in HMI designs. Rich connectivity - dual Ethernet, CAN FD, USB and audio interfaces - targets industrial gateways, operator terminals and graphics panels.
Typical applications include industrial HMI panels, edge gateways, building automation controllers and POS/graphics terminals where an LCD-TFT controller and dual Ethernet eliminate external bridge chips.
Design consideration: budget for LPDDR2/LPDDR3 routing length matching on the 16-bit DRAM interface early, as the TFBGA361 ball map constrains trace escape.
This page synthesizes distributor pricing, drop-in same-family alternatives, and practical design notes not found in the manufacturer datasheet.
Drop-in alternatives for STM32MP135AAC3 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
STM32MP135AAF3
β Drop-Inπ Reference alternative (not in catalog)
STM32MP135AAE3
β Drop-Inπ Reference alternative (not in catalog)
STM32MP135AAG3
β Drop-Inπ Reference alternative (not in catalog)
STM32MP133AAC3
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
STM32MP131AAC3
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
STM32MP135AAC3 Maximum Ratings & Electrical Characteristics
| Core | Arm 32-bit Cortex-A7 with NEON and FPU |
| Core Frequency (series) | Up to 1 GHz |
| Speed Grade (AAC3) | A speed grade (650 MHz per ST eStore listing of A-grade STM32MP135 parts) |
| Display Interface | LCD-TFT controller |
| Camera Interface | Parallel camera interface |
| Ethernet | 2x Ethernet MAC |
| CAN | 2x CAN FD |
| ADC | 2x ADC (12-bit) |
| Timers | 24 timers |
| External Memory Support | JEDEC LPDDR2 (JESD209-2E) and LPDDR3 (JESD209-3B), 16-bit interface |
| DRAM Data Width | Programmable full (16-bit) or half (8-bit) |
| DRAM QoS | Three traffic classes on read, two on write |
| Package | TFBGA361 |
| Mounting Type | Surface Mount |
STM32MP135AAC3 tfbga361 Pin Configuration Guide
Pin configuration for STM32MP135AAC3 (tfbga361 package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for STM32MP135AAC3.
Refer to the datasheet for full pin configuration.
Typical Applications
STM32MP135AAC3 is suitable for 6 applications: Industrial HMI Touch Panels, Industrial IoT Edge Gateways, Smart Building Controllers, Machine Vision Inspection, POS and Graphics Terminals, Audio and Communication Equipment.
Industrial HMI Touch Panels
The STM32MP135AAC3 fits industrial operator panels because its integrated LCD-TFT controller drives displays directly from the Cortex-A7 core without an external display bridge, while the parallel camera interface supports vision-based operator verification. Running Linux from LPDDR2/LPDDR3 memory (JEDEC JESD209-2E/209-3B compliant, 16-bit interface with three-class read QoS) provides the GUI framework headroom that MCUs lack, and the memory scheduler keeps display refresh deterministic under concurrent network traffic. With 2x Ethernet MACs and 2x CAN FD on-chip, the panel connects to both factory IT networks and field buses natively. Designers should route the DRAM bus with length-matched traces escaping the TFBGA361 ball field and use 1% tolerance feedback for DRAM termination.
Recommended
Industrial IoT Edge Gateways
The STM32MP135AAC3 serves edge gateway designs where dual Ethernet enables daisy-chained network topologies and protocol translation between IT and OT domains. The Cortex-A7 core runs protocol stacks (Modbus, OPC UA frontends, MQTT) under Linux, while 2x CAN FD controllers bridge legacy fieldbus devices without external controllers. The 24 timers and 2x ADCs handle local acquisition and PWM outputs at the edge, reducing round trips to the cloud. JEDEC LPDDR2/LPDDR3 support with QoS-graded traffic classes maintains latency bounds when network bursts coincide with data logging. Placed between an isolated PHY pair and the CAN transceivers, the MPU consolidates what previously required an MPU plus an MCU companion, cutting BOM count and board area in the TFBGA361 footprint.
Recommended
Smart Building Controllers
Building automation controllers benefit from the STM32MP135AAC3's mix of display output, fieldbus and analog integration. The LCD-TFT controller drives wall-panel status screens; 2x CAN FD connects to sensors and actuators on KNX-style or CANopen-style buses; and the 2x 12-bit ADCs sample environmental analog sensors directly, eliminating an external ADC chip. The Cortex-A7 core, part of a family clocked up to 1 GHz, runs the control application under Linux with spare headroom for local analytics. LPDDR2/LPDDR3 memory (16-bit, programmable half-width for cost-reduced variants) provides sufficient bandwidth for graphics plus logging simultaneously thanks to the three-class read QoS scheduler. Industrial temperature ordering grades suit unconditioned riser and rooftop enclosures.
Recommended
Machine Vision Inspection
The parallel camera interface on the STM32MP135AAC3 accepts image sensor data directly, and the Cortex-A7 core with NEON SIMD accelerates preprocessing such as debayering, thresholding and simple defect classification under Linux. The LCD-TFT controller displays live inspection output to an operator monitor, while 2x Ethernet streams results to the factory MES system - all on one chip. The DRAM subsystem is the critical enabler: JEDEC LPDDR2/LPDDR3 on the 16-bit interface with the advanced SDRAM scheduler and three read traffic classes keeps frame buffers and algorithm working sets from starving each other. QoS configuration should assign the camera DMA path the highest read class. The TFBGA361 package requires careful DRAM length matching for stable high-bandwidth operation.
Recommended
POS and Graphics Terminals
Point-of-sale and graphics terminals leverage the STM32MP135AAC3's single-chip integration of display, networking and peripherals to reduce system cost versus discrete processor-plus-bridge designs. The LCD-TFT controller renders UI graphics; the Ethernet MAC links to store back-office networks; and the parallel camera interface supports barcode or QR capture without a dedicated scanner chipset. Linux on the Cortex-A7 (family up to 1 GHz) supports modern application frameworks, while LPDDR3 over the 16-bit JEDEC-compliant interface provides the bandwidth the UI stack demands; the programmable 8-bit half-width option allows a cost-down variant of the same PCB. Designers should budget DRAM bandwidth between display refresh and network throughput using the controller's QoS traffic classes.
Recommended
Audio and Communication Equipment
The STM32MP135 family integrates audio interfaces (per the ST datasheet headline: audio alongside LCD-TFT, camera, 2x ETH, 2x CAN FD, 2x ADC and 24 timers), making the STM32MP135AAC3 suitable for intercom masters, PA controllers and networked audio endpoints. The Cortex-A7 runs the audio application and network stack under Linux, while dedicated audio paths connect to external codecs for low-jitter capture and playback. Dual Ethernet supports redundant audio-network topologies, and CAN FD links to paging or control subsystems in industrial plants. The DRAM controller's QoS arbitration protects audio DMA latency against display and network traffic - assign the audio stream a high read class. Industrial temperature grades cover installed-equipment environments per the ordering code.
Recommended
Recommended Products Summary
Engineering reference data for STM32MP135AAC3 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | STM32MP135AAF3 | STM32MP135AAE3 | STM32MP135AAG3 | STM32MP133AAC3 | STM32MP131AAC3 |
|---|---|---|---|---|---|---|
| Package | TFBGA361 | TFBGA361 family - same footprint class | TFBGA361 family - same footprint class | TFBGA361 family - same footprint class | TFBGA361 - same | TFBGA361 - same |
| Brand | STMicroelectronics | STMicroelectronics | STMicroelectronics | STMicroelectronics | STMicroelectronics | STMicroelectronics |
| Core | 1x Arm Cortex-A7 (family up to 1 GHz) | 1x Arm Cortex-A7 | 1x Arm Cortex-A7 (650 MHz per ST eStore) | 1x Arm Cortex-A7 | 1x Arm Cortex-A7 | 1x Arm Cortex-A7 |
| CAN FD Controllers | 2x | 2x | 2x | 2x | 2x (family feature) | Reduced (entry line) |
| External DRAM Support | LPDDR2 (JESD209-2E) / LPDDR3 (JESD209-3B), 16-bit | LPDDR2/LPDDR3 16-bit | LPDDR2/LPDDR3 16-bit | LPDDR2/LPDDR3 16-bit | LPDDR2/LPDDR3 16-bit | LPDDR2/LPDDR3 16-bit |
Key Differentiators
- Full peripheral integration on one die (vs STM32MP131AAC3)
- QoS-graded DRAM scheduler (vs STM32MP133AAC3)
- Same-family second sourcing without redesign (vs STM32MP135AAE3)
Design Notes
The LPDDR2/LPDDR3 interface is the highest-risk area of an STM32MP135AAC3 layout. Route the 16-bit DRAM bus with matched trace lengths within the TFBGA361 escape constraints, keep the DRAM within roughly 30 mm of the balls where possible, and follow the length-matching tables in the ST datasheet and AN-styled hardware development application notes from ST. Use a solid, unbroken reference plane under the DRAM bus and series-terminate clock/address lines per the ST reference design (STM32MP135F-DK style layouts). Do not swap data-bit ordering casually - the controller calibration assumes the datasheet ball map.
The STM32MP13 family requires a multi-rail power tree (core VDDCORE, DDR rails, and IO rails) with correct sequencing. ST provides PMIC solutions such as the STPMIC1 used on STM32MP1 discovery boards, which handles sequencing and DDR termination rails. Estimated: at 650 MHz-class operation on the A speed grade, core current is on the order of hundreds of milliamps - confirm exact values from the datasheet electrical characteristics table rather than estimating. Decouple each supply ball group with the capacitor network shown in the ST reference design to avoid DDR eye-diagram margin loss.
Two frequent mistakes: (1) treating the 'up to 1 GHz' family headline as the AAC3's guaranteed frequency - the ordering code's speed-grade letter determines the qualified clock, so verify against the current ST datasheet before setting clock tree budgets; (2) omitting boot media redundancy - the STM32MP1 boot ROM supports multiple boot sources (eMMC, SD, NAND, serial), and production units should pin the boot pins and fuse OTP settings deliberately. Also enable the DRAM scheduler QoS classes early; default equal-priority arbitration can starve display or network DMA under load.
Compliance Information
Compliance declarations for the specific STM32MP135AAC3 ordering code were not present in the retrieved web data. Confirm RoHS/REACH status on the official ST product page before regulated-market production.
