STM32MP135FAC3 - 1GHz Cortex-A7 MPU | STMicroelectronics
MPN: STM32MP135FAC3 β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $10.8 | $10.80 |
| 10 | $10.26 | $102.60 |
| 100 | $9.72 | $972.00 |
| 500 | $9.18 | $4,590.00 |
| 1,000 | $8.64 | $8,640.00 |
STM32MP135FAC3 Overview
An MPU (microprocessor unit) sits at the top of the embedded processing hierarchy, above microcontrollers: unlike an MCU that runs code from internal flash, an MPU executes a full operating system such as Linux from external DRAM and storage. The STM32MP135 belongs to STMicroelectronics STM32MP1 family of Arm-based MPUs, which combine application-class Cortex-A compute with STM32 ecosystem tooling and peripherals.
Key features of the STM32MP135FAC3 include the 1 GHz Cortex-A7 core (the top speed grade of the family), the STM32MP13x memory controller supporting JEDEC LPDDR2 (JESD209-2E), LPDDR3 (JESD209-3B), LPDDR and DDR3 SDRAM with a programmable 16-bit full or 8-bit half data width, and an advanced memory scheduler with SDRAM command generation and QoS support offering three read traffic classes and two write traffic classes.
The integrated DDR subsystem means designers can attach cost-effective DRAM directly, while the advanced scheduler preserves real-time behavior under mixed traffic loads - important for HMI, gateways, and control nodes running Linux. As a member of the STM32MP1 series, it is supported by the STM32Cube ecosystem, OpenSTLinux distribution, and STM32CubeMX configuration tools.
Typical applications include industrial HMI panels, IoT gateways, building automation controllers, and embedded Linux devices where a single cost-optimized Cortex-A7 core with high clock speed is sufficient.
When designing the DDR3 interface, follow the ST reference design for trace length matching and termination, and verify boot media (eMMC, SD, NAND, or serial NOR) selection against the STM32MP135 boot pins.
This page adds value beyond the datasheet by synthesizing distributor pricing context, drop-in same-family alternatives, and practical design notes for STM32MP135FAC3 selection and sourcing.
Drop-in alternatives for STM32MP135FAC3 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with STM32MP135FAC3 (same form factor and footprint) β differing in Core.
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Request AlternativesSTM32MP135FAC3 Maximum Ratings & Electrical Characteristics
| Core | Arm Cortex-A7 32-bit RISC |
| Core Count | 1 |
| Maximum Clock Frequency | 1 GHz |
| DRAM Support | LPDDR2, LPDDR3, LPDDR, DDR3 |
| DRAM Interface Width | 16-bit full / 8-bit half (programmable) |
| LPDDR2 Compliance | JEDEC JESD209-2E |
| LPDDR3 Compliance | JEDEC JESD209-3B |
| Memory Controller QoS | 3 read / 2 write traffic classes |
| Mounting Type | Surface Mount |
| Product Family | STM32MP1 (STM32MP135) |
| Series Status | Active |
STM32MP135FAC3 standard Pin Configuration Guide
Pin configuration for STM32MP135FAC3 (standard package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for STM32MP135FAC3.
Refer to the datasheet for full pin configuration.
Typical Applications
STM32MP135FAC3 is suitable for 6 applications: Industrial HMI Panels, IoT Gateways, Building Automation Controllers, Embedded Linux Edge Devices, Test and Measurement Instruments, Medical Point-of-Care Devices.
Industrial HMI Panels
Human-machine interface panels need enough CPU headroom to render graphics on touch displays while polling field I/O in real time. The STM32MP135FAC3 fits this role with its 1 GHz Cortex-A7 core, which comfortably drives a Linux GUI stack (Qt or similar) from OpenSTLinux, while the DDR controller's QoS scheduler (three read and two write traffic classes) keeps display refresh and control traffic isolated so screen updates never starve fieldbus handling. The LPDDR3/DDR3 16-bit interface provides the bandwidth a framebuffer requires at low DRAM cost. Recommended practice is 16-bit DDR3 with the display on the LTDC-class output and touch over I2C, using the STM32MP135F-DK as the software starting reference.
Recommended
IoT Gateways
Industrial and building IoT gateways aggregate fieldbuses, radios, and cloud uplinks, which demands a Linux-class processor with flexible connectivity. The STM32MP135FAC3 addresses this with its 1 GHz Cortex-A7 core running OpenSTLinux, generous peripheral set for UART/SPI/I2C expansion, and a DDR controller supporting cost-effective 16-bit DDR3 or LPDDR2 per JEDEC JESD209-2E/209-3B. The advanced SDRAM scheduler sustains responsive packet forwarding even when bursty flash or display traffic competes for bandwidth. Designers typically pair the MPU with an eMMC for the root filesystem and a Wi-Fi/BLE or LoRa module on SDIO/SPI, keeping the bill of materials compact for wall-mounted or DIN-rail enclosures.
Recommended
Building Automation Controllers
Building automation controllers (BACnet/KNX gateways, room controllers) benefit from a single cost-optimized Linux MPU rather than a premium dual-core device. The STM32MP135FAC3's 1 GHz Cortex-A7 handles protocol stacks, web servers, and scheduling logic with margin, while its 16-bit LPDDR interface lowers DRAM cost in high-volume deployments. The memory controller's programmable full (16-bit) or half (8-bit) data width lets the same PCB platform scale across product tiers, from entry controllers (8-bit LPDDR) to premium models (16-bit DDR3) without a board respin of the power tree or core layout. Industrial temperature grades in the STM32MP135 family support unconditioned electrical rooms.
Recommended
Embedded Linux Edge Devices
Edge devices performing local data preprocessing - protocol translation, sensor fusion, lightweight analytics - need deterministic memory behavior as much as raw CPU speed. The STM32MP135FAC3 contributes both: a 1 GHz Cortex-A7 for computation and a DDR subsystem whose advanced scheduler and SDRAM command generator provide three QoS read traffic classes and two write classes, so real-time acquisition is never blocked by bulk logging writes. The 16-bit LPDDR2/LPDDR3/DDR3 interface sustains the bandwidth for ring-buffer capture at low power compared with application processors in the same class. Firmware portability within the STM32MP135 family allows speed-grade tuning per product SKU on one PCB.
Recommended
Test and Measurement Instruments
Benchtop and portable instruments increasingly embed a Linux processor for UI, connectivity, and data logging alongside analog front ends. The STM32MP135FAC3's 1 GHz core runs instrument UI frameworks and network services (LXI/VNC-class remote access), while the QoS-managed DDR controller guarantees that ADC streaming DMA is scheduled ahead of background logging traffic - a direct benefit of its three read and two write traffic classes. Support for industrial temperature grades and the long-lifecycle STM32MP1 roadmap suit instruments with multi-year service commitments. The 16-bit DDR3 interface with JEDEC JESD209-2E/209-3B-compliant LPDDR options lets designers balance bandwidth against battery budget in portable units.
Recommended
Medical Point-of-Care Devices
Point-of-care terminals, portable analyzers, and patient-data displays require a responsive Linux UI, secure data handling, and dependable supply continuity. The STM32MP135FAC3's 1 GHz Cortex-A7 drives GUI and network stacks, while its DDR controller's QoS scheduling keeps measurement pipelines responsive under UI load. The STM32MP1 family's documentation depth (datasheet, reference manual, OpenSTLinux distribution) shortens regulatory design-history documentation. Its 16-bit LPDDR3 interface per JEDEC JESD209-3B offers the bandwidth for waveform rendering with modest power, helping battery-operated designs meet runtime targets. Designers should select the appropriate temperature grade suffix and follow ST security documentation for patient-data protection.
Recommended
Recommended Products Summary
Engineering reference data for STM32MP135FAC3 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | STM32MP135CAF3 | STM32MP135DAG3 | STM32MP135FAG3 | STM32MP135AAC3 |
|---|---|---|---|---|---|
| Package | TFBGA361 | TFBGA361 - same | TFBGA361 - same | TFBGA361 - same | TFBGA361 - same |
| Brand | STMicroelectronics | STMicroelectronics | STMicroelectronics | STMicroelectronics | STMicroelectronics |
| Max Core Clock | 1 GHz | 650 MHz | 900 MHz | 1 GHz | 650 MHz |
| Core Architecture | 1x Arm Cortex-A7 32-bit | 1x Arm Cortex-A7 32-bit | 1x Arm Cortex-A7 32-bit | 1x Arm Cortex-A7 32-bit | 1x Arm Cortex-A7 32-bit |
| DRAM Support | LPDDR2/LPDDR3/LPDDR/DDR3, 16-bit | LPDDR2/LPDDR3/LPDDR/DDR3, 16-bit | LPDDR2/LPDDR3/LPDDR/DDR3, 16-bit | LPDDR2/LPDDR3/LPDDR/DDR3, 16-bit | LPDDR2/LPDDR3/LPDDR/DDR3, 16-bit |
| Memory QoS | 3 read / 2 write traffic classes | 3 read / 2 write traffic classes | 3 read / 2 write traffic classes | 3 read / 2 write traffic classes | 3 read / 2 write traffic classes |
| LPDDR Compliance | JESD209-2E / JESD209-3B | JESD209-2E / JESD209-3B | JESD209-2E / JESD209-3B | JESD209-2E / JESD209-3B | JESD209-2E / JESD209-3B |
Key Differentiators
- Top speed grade of the STM32MP135 family (vs STM32MP135CAF3)
- Cost-tier fallback without respin (vs STM32MP135DAC3)
- QoS-managed DDR subsystem (vs Generic Cortex-A7 MPUs)
Design Notes
The 16-bit DDR3/LPDDR3 interface on a BGA package demands careful layout: length-match address/command groups within the datasheet skew budget, keep data lanes matched per byte lane, and follow the STM32MP135 reference manual and ST application note DDR routing guidelines for termination and series resistors. Use the STM32MP135F-DK schematic as the golden reference for the power tree (core, DRAM, IO rails) and boot-mode strap resistors before finalizing your own PCB.
Estimated: an MPU of this class draws its highest current during Linux boot and DDR training; size the core and DRAM rails with headroom above the typical run-state figures in the ST datasheet power tables (exact per-rail values are in the datasheet - consult it rather than scaling from estimates). Use a PMIC or a sequenced discrete rail solution matching the datasheet power-up order, and verify rail sequencing against the datasheet to avoid DDR controller lockout at reset.
Boot media selection is set by boot pins sampled at reset - mis-strapped BOOT0/BOOT1 pins are the most common bring-up failure on STM32MP1 boards. Also confirm the exact part-number suffix: the speed grade letter (C/D/F), feature letter, and temperature digit all change what firmware and thermal margins are valid. Verify the FAC3 ordering code against the ST ordering-information table before release, since MP135 family suffixes are easy to confuse in BOMs.
Compliance Information
Compliance status not stated in the provided verified web data; consult the ST product page compliance documentation for STM32MP135FAC3 before release.
