EPM3128ATI100-5N - MAX 3000A CPLD, 128 Macrocells, TQFP-100 | Intel / Altera
MPN: EPM3128ATI100-5N β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.8 | $168.00 |
| 100 | $14.95 | $1,495.00 |
| 500 | $13.2 | $6,600.00 |
| 1,000 | $11.45 | $11,450.00 |
Drop-in alternatives for EPM3128ATI100-5N β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM3128ATC100-5N
β Drop-Inβ In Stock
$8.2 / Unit
View Datasheet βEPM3128ATC100-7N
β Drop-Inβ In Stock
$3.52 / Unit
View Datasheet βEPM3128ATC100-10N
β Drop-Inβ In Stock
$5.2 / Unit
View Datasheet βEPM3128ATI100-10N
β Drop-Inπ Reference alternative (not in catalog)
EPM3128ATC100-5
β Drop-Inβ In Stock
$15.43 / Unit
View Datasheet βEPM3128ATC100-10
β Drop-Inβ In Stock
$8.1 / Unit
View Datasheet βEPM3128ATI100-5N Maximum Ratings & Electrical Characteristics
| Family | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Macrocells | 128 |
| Logic Array Blocks (LABs) | 8 (16 macrocells per LAB) |
| User I/O Pins | 80 |
| Pin-to-Pin Delay (tPD) | 5.0 ns |
| Supply Voltage (VCCINT) | 3.3 V |
| I/O Standard | 3.3 V LVCMOS / LVTTL, 5.0 V tolerant inputs |
| Programming Method | In-System Programmable via IEEE Std. 1532 (JTAG) |
| Operating Temperature | -40C to +85C (Industrial) |
| Package | 100-pin TQFP |
| Mounting Type | Surface Mount |
| Configuration Memory | Non-volatile EEPROM |
| JTAG Support | IEEE 1149.1 boundary scan |
| RoHS Status | Compliant (lead-free TQFP package) |
EPM3128ATI100-5N Pin Configuration
| Pin 1 | I/O β General-purpose user I/O |
| Pin 2 | I/O β General-purpose user I/O |
| Pin 3 | I/O β General-purpose user I/O |
| Pin 4 | I/O β General-purpose user I/O |
| Pin 5 | I/O β General-purpose user I/O |
| Pin 6 | VCCINT β 3.3V core supply |
| Pin 7 | GND β Ground |
| Pin 8 | TDI β JTAG Test Data In |
| Pin 9 | TMS β JTAG Test Mode Select |
| Pin 10 | TCK β JTAG Test Clock |
| Pin 11 | TDO β JTAG Test Data Out |
| Pin 12 | INPUT/GCLK β Global clock input / dedicated input |
| Pin 13 | INPUT/OE1 β Global OE / dedicated input |
| Pin 14 | OE2/GCLK2 β Global OE2 / global clock 2 |
| Pin 15 | I/O β General-purpose user I/O |
| Pin 16 | I/O β General-purpose user I/O |
| Pin 17 | I/O β General-purpose user I/O |
| Pin 18 | VCCIO β 3.3V I/O supply |
| Pin 19 | GND β Ground |
| Pin 20 | I/O β General-purpose user I/O |
| Pin 21 | I/O β General-purpose user I/O |
| Pin 22 | I/O β General-purpose user I/O |
| Pin 23 | I/O β General-purpose user I/O |
| Pin 24 | I/O β General-purpose user I/O |
| Pin 25 | I/O β General-purpose user I/O |
| Pin 26 | VCCINT β 3.3V core supply |
| Pin 27 | GND β Ground |
| Pin 28 | I/O β General-purpose user I/O |
| Pin 29 | I/O β General-purpose user I/O |
| Pin 30 | I/O β General-purpose user I/O |
| Pin 31 | I/O β General-purpose user I/O |
| Pin 32 | I/O β General-purpose user I/O |
| Pin 33 | I/O β General-purpose user I/O |
| Pin 34 | VCCIO β 3.3V I/O supply |
| Pin 35 | GND β Ground |
| Pin 36 | I/O β General-purpose user I/O |
| Pin 37 | I/O β General-purpose user I/O |
| Pin 38 | I/O β General-purpose user I/O |
| Pin 39 | I/O β General-purpose user I/O |
| Pin 40 | I/O β General-purpose user I/O |
| Pin 41 | I/O β General-purpose user I/O |
| Pin 42 | I/O β General-purpose user I/O |
| Pin 43 | VCCINT β 3.3V core supply |
| Pin 44 | GND β Ground |
| Pin 45 | I/O β General-purpose user I/O |
| Pin 46 | I/O β General-purpose user I/O |
| Pin 47 | I/O β General-purpose user I/O |
| Pin 48 | I/O β General-purpose user I/O |
| Pin 49 | I/O β General-purpose user I/O |
| Pin 50 | I/O β General-purpose user I/O |
| Pin 51 | VCCIO β 3.3V I/O supply |
| Pin 52 | GND β Ground |
| Pin 53 | I/O β General-purpose user I/O |
| Pin 54 | I/O β General-purpose user I/O |
| Pin 55 | I/O β General-purpose user I/O |
| Pin 56 | I/O β General-purpose user I/O |
| Pin 57 | I/O β General-purpose user I/O |
| Pin 58 | I/O β General-purpose user I/O |
| Pin 59 | VCCINT β 3.3V core supply |
| Pin 60 | GND β Ground |
| Pin 61 | I/O β General-purpose user I/O |
| Pin 62 | I/O β General-purpose user I/O |
| Pin 63 | I/O β General-purpose user I/O |
| Pin 64 | I/O β General-purpose user I/O |
| Pin 65 | I/O β General-purpose user I/O |
| Pin 66 | I/O β General-purpose user I/O |
| Pin 67 | VCCIO β 3.3V I/O supply |
| Pin 68 | GND β Ground |
| Pin 69 | I/O β General-purpose user I/O |
| Pin 70 | I/O β General-purpose user I/O |
| Pin 71 | I/O β General-purpose user I/O |
| Pin 72 | I/O β General-purpose user I/O |
| Pin 73 | I/O β General-purpose user I/O |
| Pin 74 | I/O β General-purpose user I/O |
| Pin 75 | VCCINT β 3.3V core supply |
| Pin 76 | GND β Ground |
| Pin 77 | I/O β General-purpose user I/O |
| Pin 78 | I/O β General-purpose user I/O |
| Pin 79 | I/O β General-purpose user I/O |
| Pin 80 | I/O β General-purpose user I/O |
| Pin 81 | I/O β General-purpose user I/O |
| Pin 82 | I/O β General-purpose user I/O |
| Pin 83 | VCCIO β 3.3V I/O supply |
| Pin 84 | GND β Ground |
| Pin 85 | I/O β General-purpose user I/O |
| Pin 86 | I/O β General-purpose user I/O |
| Pin 87 | I/O β General-purpose user I/O |
| Pin 88 | I/O β General-purpose user I/O |
| Pin 89 | I/O β General-purpose user I/O |
| Pin 90 | I/O β General-purpose user I/O |
| Pin 91 | VCCINT β 3.3V core supply |
| Pin 92 | GND β Ground |
| Pin 93 | I/O β General-purpose user I/O |
| Pin 94 | I/O β General-purpose user I/O |
| Pin 95 | I/O β General-purpose user I/O |
| Pin 96 | I/O β General-purpose user I/O |
| Pin 97 | I/O β General-purpose user I/O |
| Pin 98 | I/O β General-purpose user I/O |
| Pin 99 | VCCIO β 3.3V I/O supply |
| Pin 100 | GND β Ground |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM3128ATI100-5N is suitable for 7 applications: Industrial Control Glue Logic, Microcontroller Bus Address Decoding, Peripheral Interface Bridging, Legacy 5V Interface Adaptation, State Machine and FSM Implementation, PCI Local Bus Arbiter, JTAG Chain Management and TAP Controller.
Industrial Control Glue Logic
The EPM3128ATI100-5N fits industrial control glue-logic designs because its industrial -40C to +85C temperature range tolerates factory-floor thermal stress while its 128 macrocells and 80 I/Os can replace 6-10 discrete 74HC/74LVC packages. The 5.0 ns pin-to-pin delay ensures deterministic timing for handshake and interrupt arbitration in PLC backplanes. The 5V-tolerant inputs interface directly with legacy 24V-to-5V opto-isolated signals, and non-volatile EEPROM configuration guarantees deterministic startup after power brownouts common in industrial mains environments.
Recommended
Microcontroller Bus Address Decoding
The EPM3128ATI100-5N is ideal for microcontroller bus address decoding because its 128 macrocells can decode wide address buses (24-32 bits) with a single device, eliminating cascading 74HC138/74HC139 chips. The 5.0 ns tPD meets 8-bit/16-bit MCU cycle times at 50 MHz, and the 80 I/O pins accommodate chip-select, bank-select, and wait-state generation outputs. Non-volatile configuration means chip-selects are valid at power-on, eliminating boot glitches during MCU reset. Industrial temperature grade suits automotive and outdoor embedded controllers.
Recommended
Peripheral Interface Bridging
The EPM3128ATI100-5N serves peripheral interface bridging applications well because it can simultaneously convert between parallel buses (ISA, PCI local bus), serial protocols (SPI, I2C, UART), and memory interfaces (SRAM, NOR flash) in one device. The 80 I/Os are sufficient for 16-bit data plus 24-bit address plus control signals for legacy bus bridging. 5V-tolerant inputs accept 5V peripheral signals, while 3.3V LVCMOS outputs drive modern MCUs. JTAG ISP enables firmware updates in deployed field equipment.
Recommended
Legacy 5V Interface Adaptation
The EPM3128ATI100-5N adapts legacy 5V systems because its 5V-tolerant inputs accept 5.5V signals directly without external level shifters, while its 3.3V LVCMOS outputs drive modern 3.3V ASICs, FPGAs, and microcontrollers. Open-drain outputs with external pull-ups can also drive 5V CMOS inputs per the MAX 3000A datasheet. This makes it a one-chip translator between legacy 5V peripherals and modern 3.3V logic in industrial control retrofits.
Recommended
State Machine and FSM Implementation
The EPM3128ATI100-5N implements complex state machines efficiently because each of its 128 macrocells contains a flip-flop configurable as D, T, JK, or SR with up to 32 product terms, ideal for FSM encoding. Multiple state machines can coexist in the same device, and the deterministic 5.0 ns tPD simplifies timing closure. Industrial temp grade and JTAG ISP make it suitable for deployed state-machine controllers in unmanned equipment where field re-programmability is required.
Recommended
PCI Local Bus Arbiter
The EPM3128ATI100-5N works well as a PCI local bus arbiter because its 5.0 ns tPD meets PCI 33 MHz timing budgets for grant/req handshake, and the 80 I/Os handle multiple REQ/GNT pairs plus sideband signals. Non-volatile EEPROM configuration is critical for bus arbitration logic where power-on state must be deterministic. Industrial temp grade allows deployment in PCI-based industrial PCs operating in uncontrolled environments.
Recommended
JTAG Chain Management and TAP Controller
The EPM3128ATI100-5N serves JTAG chain management because its native IEEE 1149.1 boundary-scan support lets it implement TAP controllers, JTAG multiplexers, and chain segmenters that switch JTAG access between multiple downstream devices. Industrial temp grade ensures reliable JTAG operation in test fixtures deployed on production lines. 5.0 ns timing meets TCK frequencies up to 200 MHz for high-speed programming.
Recommended
Recommended Products Summary
Engineering reference data for EPM3128ATI100-5N β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM3128ATC100-5N | EPM3128ATC100-7N | EPM3128ATC100-10N | EPM3128ATI100-10N |
|---|---|---|---|---|---|
| Brand | Intel (formerly Altera) | Intel | Intel | Intel | Intel |
| Package | TQFP-100 | TQFP-100 | TQFP-100 | TQFP-100 | TQFP-100 |
| Macrocells | 128 | 128 | 128 | 128 | 128 |
| User I/Os | 80 | 80 | 80 | 80 | 80 |
| Pin-to-Pin Delay (tPD) | 5.0 ns | 5.0 ns | 7.5 ns | 10.0 ns | 10.0 ns |
| Operating Temperature | -40C to +85C (Industrial) | 0C to +70C (Commercial) | 0C to +70C (Commercial) | 0C to +70C (Commercial) | -40C to +85C (Industrial) |
| Supply Voltage | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| Programming Method | JTAG (IEEE 1532) | JTAG (IEEE 1532) | JTAG (IEEE 1532) | JTAG (IEEE 1532) | JTAG (IEEE 1532) |
| RoHS Status | Compliant | Compliant | Compliant | Compliant | Compliant |
Key Differentiators
- Industrial temperature grade with full 5.0 ns speed (vs EPM3128ATI100-10N)
- Same-footprint faster speed grade compared to commercial-temp parts (vs EPM3128ATC100-5N)
- Higher macrocell density vs MAX 3000A 64-macrocell parts (vs EPM3064ATI100-10N)
Design Notes
The MAX 3000A CPLD requires both VCCINT (3.3V core) and VCCIO (3.3V I/O) supplies. Decouple each VCC pin with a 0.1uF ceramic capacitor placed within 5mm of the pin, plus a single 10uF bulk capacitor per device. Estimated: at 50 MHz toggle rate, typical Icc is approximately 50 mA; static Icc (no toggle) is below 10 mA. The POR circuit requires VCC to rise monotonically - if a brownout condition is possible, add a supervisor IC to reset the device.
Route the JTAG signals (TCK, TMS, TDI, TDO) as a single chain with stub-free traces. Keep TCK trace under 100mm and isolate it from switching signals with ground guard traces. Place a 10k pull-up on TCK and TMS to prevent floating JTAG state during power-up. Reserve a dedicated 2x5 or 2x7 header for the Altera ByteBlaster or USB-Blaster programming cable - do not share the JTAG pins with other functions.
The MAX 3000A has 5V-tolerant inputs but 3.3V outputs. When driving 5V-only inputs, use a discrete level shifter (e.g., 74HCT125 buffer) or configure the CPLD output as open-drain with a pull-up to 5V rail - the MAX 3000A datasheet permits open-drain output with external pull-up to 5.0V supply. Avoid capacitive loads above 50pF on high-speed outputs to prevent rise-time degradation.
Do not apply 5V to any VCCIO or VCCINT pin - only inputs are 5V-tolerant. Ensure the JTAG chain order matches the Quartus pin assignment file - reversing TDI/TDO prevents programming without damaging the device. When migrating between speed grades (-5, -7, -10), recompile the Quartus design for the new tPD to avoid hold-time violations. The 'N' suffix indicates lead-free / RoHS compliant packaging.
Compliance Information
RoHS compliant per Altera / Intel product page. The 'N' suffix denotes lead-free matte-tin plating. Halogen-free status not explicitly documented - assumed standard for Altera lead-free parts. AEC-Q100 not qualified - this part is industrial grade, not automotive grade.
