EPM7128AETC100-5N - 128-Macrocell MAX 7000A CPLD, 5ns | Intel / Altera
N.º da peça: EPM7128AETC100-5N ✓ Ativo| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $11.2 | $11,20 |
| 10 | $10.08 | $100,80 |
| 100 | $8.95 | $895,00 |
| 500 | $7.95 | $3.975,00 |
| 1.000 | $6.85 | $6.850,00 |
EPM7128AETC100-5N Visão geral
What is a CPLD? A Complex Programmable Logic Device is a non-volatile, instantly-on programmable logic device that bridges the gap between small PAL/GAL devices and larger FPGAs. It sits in the programmable logic hierarchy between simple PLDs (PAL/GAL) and FPGAs, offering fast deterministic timing, instant-on behavior from on-chip EEPROM/Flash, and lower unit cost for glue-logic applications. The MAX 7000A architecture uses an Enhanced EEPROM process with the Altera second-generation MAX interconnect, providing predictable timing paths and 100% routability.
Key features of the EPM7128AETC100-5N include a maximum operating frequency of approximately 192.3 MHz, four I/O banks supporting 5.0V tolerant inputs when VCCIO is at 3.3V, in-system programmability via JTAG (IEEE Std. 1149.1), and MultiVolt I/O for interfacing with 5.0V, 3.3V, and 2.5V logic. The 100-pin TQFP package offers a compact surface-mount footprint suited to industrial control and communications glue-logic designs.
Architecturally, the device integrates 128 macrocells, each composed of a programmable AND/OR/expander array and a configurable flip-flop with independent programmable clock, enable, clear, and preset control. The I/O structure includes 3.3V PCI-compliant drivers when VCCIO is tied to 3.3V, and open-drain output options for bus interface applications. The JTAG boundary-scan test circuitry supports IEEE 1149.1 boundary-scan testing and in-system configuration.
Typical applications of the EPM7128AETC100-5N span industrial glue logic, address decoding for microprocessors and DSPs, bus interfacing and voltage translation between 5V and 3.3V domains, peripheral control in embedded systems, and state-machine-driven control logic. Designers choose the EPM7128A when they need fast deterministic timing, instant-on non-volatile configuration, and 5V-tolerant I/O in a moderate-density package.
A key design consideration is power sequencing: the Altera datasheet requires VCC to rise monotonically for the EPM7128A family to avoid spurious configuration events. Designers should also observe the 5.0V input tolerance window (VCCIO = 3.3V) and choose 3.3V or 2.5V output drive levels based on the downstream logic family.
This page synthesizes distributor pricing, drop-in alternatives from the MAX 7000A family and cross-brand pin-compatible CPLDs, and practical design notes not assembled on the manufacturer datasheet.
Alternativas drop-in para EPM7128AETC100-5N — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Variantes desta série
Modelos da mesma série compatíveis como drop-in com EPM7128AETC100-5N (mesmo formato e footprint) — diferindo em Package, Operating Temperature, Usable Gates, Logic Array Blocks (LABs), Process Technology.
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
EPM7128AETC100-7
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
EPM7128AETC100-10N
✅ Drop-In✓ Em estoque
$9.95 / unidade
Ver ficha técnica →EPM7128AETC100-5
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
EPM7128AETC100-10
✅ Drop-In✓ Em estoque
$13.85 / unidade
Ver ficha técnica →EPM7128AETC100-5N Classificações máximas e características elétricas
| Family | MAX 7000A |
| Device Type | CPLD - Complex Programmable Logic Device |
| Macrocells | 128 |
| User I/Os | 84 |
| Logic Gates (typical) | 2,500 |
| Pin-to-Pin Logic Delay (tPD) | 5 ns |
| Maximum Operating Frequency | 192.3 MHz |
| Core Supply Voltage (VCCINT) | 3.3 V |
| I/O Bank Supply Voltage (VCCIO) | 3.3 V or 2.5 V |
| 5V Tolerant Inputs | Yes (when VCCIO = 3.3 V) |
| Programmable Logic Type | EEPROM-based, in-system programmable |
| Programming Interface | JTAG (IEEE Std. 1149.1) |
| Encapsulamento | 100-pin TQFP |
| Tipo de montagem | Surface Mount |
| Temperatura de operação | 0C to +70C (commercial) |
| Status RoHS | Compliant |
Configuração de pinos do EPM7128AETC100-5N
| Pino 1 | I/O — User I/O pin (macrocell 84) |
| Pino 2 | I/O — User I/O pin (macrocell 83) |
| Pino 3 | I/O — User I/O pin (macrocell 82) |
| Pino 4 | I/O — User I/O pin (macrocell 81) |
| Pino 5 | I/O — User I/O pin (macrocell 80) |
| Pino 6 | I/O — User I/O pin (macrocell 79) |
| Pino 7 | I/O — User I/O pin (macrocell 78) |
| Pino 8 | I/O — User I/O pin (macrocell 77) |
| Pino 9 | VCCINT — Core supply voltage (3.3 V) |
| Pino 10 | I/O — User I/O pin (macrocell 76) |
| Pino 11 | I/O — User I/O pin (macrocell 75) |
| Pino 12 | I/O — User I/O pin (macrocell 74) |
| Pino 13 | I/O — User I/O pin (macrocell 73) |
| Pino 14 | I/O — User I/O pin (macrocell 72) |
| Pino 15 | I/O — User I/O pin (macrocell 71) |
| Pino 16 | GND — Ground |
| Pino 17 | I/O — User I/O pin (macrocell 70) |
| Pino 18 | I/O — User I/O pin (macrocell 69) |
| Pino 19 | I/O — User I/O pin (macrocell 68) |
| Pino 20 | I/O — User I/O pin (macrocell 67) |
| Pino 21 | I/O — User I/O pin (macrocell 66) |
| Pino 22 | I/O — User I/O pin (macrocell 65) |
| Pino 23 | I/O — User I/O pin (macrocell 64) |
| Pino 24 | GND — Ground |
| Pino 25 | I/O — User I/O pin (macrocell 63) |
| Pino 26 | I/O — User I/O pin (macrocell 62) |
| Pino 27 | I/O — User I/O pin (macrocell 61) |
| Pino 28 | I/O — User I/O pin (macrocell 60) |
| Pino 29 | I/O — User I/O pin (macrocell 59) |
| Pino 30 | I/O — User I/O pin (macrocell 58) |
| Pino 31 | I/O — User I/O pin (macrocell 57) |
| Pino 32 | VCCIO — I/O bank supply voltage (3.3 V or 2.5 V) |
| Pino 33 | I/O — User I/O pin (macrocell 56) |
| Pino 34 | I/O — User I/O pin (macrocell 55) |
| Pino 35 | I/O — User I/O pin (macrocell 54) |
| Pino 36 | I/O — User I/O pin (macrocell 53) |
| Pino 37 | I/O — User I/O pin (macrocell 52) |
| Pino 38 | I/O — User I/O pin (macrocell 51) |
| Pino 39 | I/O — User I/O pin (macrocell 50) |
| Pino 40 | GND — Ground |
| Pino 41 | I/O — User I/O pin (macrocell 49) |
| Pino 42 | I/O — User I/O pin (macrocell 48) |
| Pino 43 | I/O — User I/O pin (macrocell 47) |
| Pino 44 | I/O — User I/O pin (macrocell 46) |
| Pino 45 | I/O — User I/O pin (macrocell 45) |
| Pino 46 | I/O — User I/O pin (macrocell 44) |
| Pino 47 | I/O — User I/O pin (macrocell 43) |
| Pino 48 | VCCINT — Core supply voltage (3.3 V) |
| Pino 49 | I/O — User I/O pin (macrocell 42) |
| Pino 50 | I/O — User I/O pin (macrocell 41) |
| Pino 51 | I/O — User I/O pin (macrocell 40) |
| Pino 52 | I/O — User I/O pin (macrocell 39) |
| Pino 53 | I/O — User I/O pin (macrocell 38) |
| Pino 54 | I/O — User I/O pin (macrocell 37) |
| Pino 55 | I/O — User I/O pin (macrocell 36) |
| Pino 56 | GND — Ground |
| Pino 57 | I/O — User I/O pin (macrocell 35) |
| Pino 58 | I/O — User I/O pin (macrocell 34) |
| Pino 59 | I/O — User I/O pin (macrocell 33) |
| Pino 60 | I/O — User I/O pin (macrocell 32) |
| Pino 61 | I/O — User I/O pin (macrocell 31) |
| Pino 62 | I/O — User I/O pin (macrocell 30) |
| Pino 63 | I/O — User I/O pin (macrocell 29) |
| Pino 64 | VCCIO — I/O bank supply voltage (3.3 V or 2.5 V) |
| Pino 65 | I/O — User I/O pin (macrocell 28) |
| Pino 66 | I/O — User I/O pin (macrocell 27) |
| Pino 67 | I/O — User I/O pin (macrocell 26) |
| Pino 68 | I/O — User I/O pin (macrocell 25) |
| Pino 69 | I/O — User I/O pin (macrocell 24) |
| Pino 70 | I/O — User I/O pin (macrocell 23) |
| Pino 71 | I/O — User I/O pin (macrocell 22) |
| Pino 72 | GND — Ground |
| Pino 73 | I/O — User I/O pin (macrocell 21) |
| Pino 74 | I/O — User I/O pin (macrocell 20) |
| Pino 75 | I/O — User I/O pin (macrocell 19) |
| Pino 76 | I/O — User I/O pin (macrocell 18) |
| Pino 77 | I/O — User I/O pin (macrocell 17) |
| Pino 78 | I/O — User I/O pin (macrocell 16) |
| Pino 79 | I/O — User I/O pin (macrocell 15) |
| Pino 80 | VCCINT — Core supply voltage (3.3 V) |
| Pino 81 | I/O — User I/O pin (macrocell 14) |
| Pino 82 | I/O — User I/O pin (macrocell 13) |
| Pino 83 | I/O — User I/O pin (macrocell 12) |
| Pino 84 | I/O — User I/O pin (macrocell 11) |
| Pino 85 | I/O — User I/O pin (macrocell 10) |
| Pino 86 | I/O — User I/O pin (macrocell 9) |
| Pino 87 | I/O — User I/O pin (macrocell 8) |
| Pino 88 | GND — Ground |
| Pino 89 | I/O — User I/O pin (macrocell 7) |
| Pino 90 | I/O — User I/O pin (macrocell 6) |
| Pino 91 | I/O — User I/O pin (macrocell 5) |
| Pino 92 | I/O — User I/O pin (macrocell 4) |
| Pino 93 | I/O — User I/O pin (macrocell 3) |
| Pino 94 | I/O — User I/O pin (macrocell 2) |
| Pino 95 | I/O — User I/O pin (macrocell 1) |
| Pino 96 | VCCIO — I/O bank supply voltage (3.3 V or 2.5 V) |
| Pino 97 | TDI — JTAG Test Data In |
| Pino 98 | TMS — JTAG Test Mode Select |
| Pino 99 | TCK — JTAG Test Clock |
| Pino 100 | TDO — JTAG Test Data Out |
Aplicações típicas
EPM7128AETC100-5N é adequado para 6 aplicaçãos: Industrial Glue Logic and Address Decoding, 5V to 3.3V Bus Voltage Translation Bridge, Embedded Peripheral Control and State Machines, Communications Backplane Glue and TDM Switching, PCI Bus Interface and Arbiter Logic, Legacy System Modernization and I/O Expansion.
Industrial Glue Logic and Address Decoding
The EPM7128AETC100-5N is widely used as address-decoding glue logic in 8/16/32-bit microprocessor and DSP systems, where its 5 ns tPD and 84 user I/Os can replace stacks of 74LS/74HC discrete decoder gates. The 128 macrocells can implement multiple independent chip-select functions, register-based state machines, and wait-state generators in a single non-volatile device that powers up instantly from on-chip EEPROM - critical for industrial PLC backplanes where predictable boot behavior is mandatory. Its 5V-tolerant inputs (when VCCIO = 3.3V) allow direct interfacing to legacy 5V peripheral buses without external level shifters, and the JTAG ISP support enables field firmware updates without removing the board from service.
Recomendado
5V to 3.3V Bus Voltage Translation Bridge
The EPM7128AETC100-5N operates as a bidirectional voltage-translation bridge between 5V legacy microcontrollers and 3.3V modern peripherals, exploiting its MultiVolt I/O architecture where VCCIO can be tied to 3.3V while inputs tolerate 5V signals. With 84 I/Os and 5 ns propagation delay, it can buffer an entire 16-bit data bus plus address and control signals in a single chip, replacing discrete bus-switch ICs (e.g., 74LVTH245) with programmable direction control per bit. The 100-pin TQFP footprint gives ample headroom for 32-bit datapaths and interrupt steering, and the JTAG ISP allows designers to redefine the direction map in the field.
Recomendado
Embedded Peripheral Control and State Machines
Designers use the EPM7128AETC100-5N to implement custom peripheral controllers, FIFO hand-shaking logic, and complex multi-state control sequences that would otherwise require a small FPGA or a large discrete state-machine board. The 128 macrocells and 192.3 MHz Fmax comfortably handle encoder quadrature decoding, stepper-motor pulse trains, and PWM generation at industrial switching frequencies. Deterministic 5 ns timing paths allow the part to replace small PAL/GAL arrays and 22V10 devices while offering more I/O and instant-on EEPROM configuration - no boot PROM or external flash required, which reduces PCB area and BOM cost.
Recomendado
Communications Backplane Glue and TDM Switching
In telecom and datacom backplanes, the EPM7128AETC100-5N serves as a programmable TDM (Time-Division Multiplexing) switch, frame-alignment engine, and clock-distribution buffer, where the 5 ns propagation delay is fast enough to retime E1/T1 or JESD204B-aligned data without adding measurable jitter. The 84 I/Os handle multiple serial streams plus framing overhead, while the four I/O banks allow direct interfacing to 3.3V PHY chips and 2.5V line-interface units from a single CPLD. In-system programmability lets the same hardware platform be repurposed across product variants by simply reloading the EEPROM image via JTAG.
Recomendado
PCI Bus Interface and Arbiter Logic
The EPM7128AETC100-5N implements PCI bus target devices, bus arbiters, and configuration-space registers in legacy 33 MHz PCI add-in cards. When VCCIO is tied to 3.3V the I/O drivers meet the PCI 3.3V signalling standard directly, and the 128 macrocells can hold the full PCI target state machine plus interrupt acknowledge and parity logic. Compared to a dedicated PCI interface ASIC, the CPLD offers full design flexibility and field firmware updates via JTAG, while the 5 ns tPD comfortably meets the 33 MHz PCI clock-period budget of 30 ns across the CPLD's combinational paths.
Recomendado
Legacy System Modernization and I/O Expansion
When modernizing 8051, 68k, or other legacy CPU platforms, designers drop in the EPM7128AETC100-5N to add USB, SD-card, or LCD interfaces that the original processor could not natively drive. The 84 I/Os can host an 8/16-bit parallel bus plus chip-select, read/write, and interrupt lines for multiple peripherals, while the EEPROM-based configuration means the firmware lives with the hardware. The 100-pin TQFP footprint and 5V-tolerant inputs ease retrofitting into older 5V-system boards, and the JTAG port allows in-circuit reprogramming during bring-up.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para EPM7128AETC100-5N — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | EPM7128AETC100-7 | EPM7128AETC100-10N | EPM7128AETC100-5 | EPM7128AELC84-10N |
|---|---|---|---|---|---|
| Brand | Intel (formerly Altera) | Intel | Intel | Intel | Intel |
| Package | TQFP-100 | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same | PLCC-84 - different |
| Family | MAX 7000A | MAX 7000A | MAX 7000A | MAX 7000A | MAX 7000A |
| Pin-to-Pin Delay (tPD) | 5 ns | 7 ns | 10 ns | 5 ns | 10 ns |
| Macrocells | 128 | 128 | 128 | 128 | 128 |
| User I/Os | 84 | 84 | 84 | 84 | 68 |
| Core Voltage (VCCINT) | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| Programming Interface | JTAG (IEEE 1149.1) | JTAG (IEEE 1149.1) | JTAG (IEEE 1149.1) | JTAG (IEEE 1149.1) | JTAG (IEEE 1149.1) |
Principais diferenciais
- Fastest speed grade in the EPM7128AE TQFP-100 family (vs EPM7128AETC100-7)
- Same die, RoHS-compliant ("N" suffix) production material (vs EPM7128AETC100-5)
- TQFP-100 footprint with 84 user I/Os (vs EPM7128AELC84-10N)
Notas de projeto
According to the Altera datasheet Operating Requirements section, VCC must rise monotonically for EPM7128A and EPM7256A devices - a non-monotonic ramp can corrupt the on-chip EEPROM configuration or trigger spurious JTAG operations. Use a supervisor IC or a well-decoupled linear regulator with controlled rise time between 1 ms and 100 ms; avoid slow RC ramps longer than 100 ms or pulsed / stepped power-up sequences. Decouple each VCCINT and VCCIO pin with a 0.1 uF X7R ceramic placed within 5 mm of the lead, plus a bulk 10 uF tantalum or ceramic near the device.
The MAX 7000A datasheet specifies minimum DC input voltage of -0.5 V; during transitions inputs may undershoot to -2.0 V only for input currents less than 100 mA and periods shorter than 20 ns. Add a 33 ohm series resistor and a clamp diode to GND on any input that is hot-plugged or that connects to a long PCB trace to prevent EOS damage. Also note that VCCIO below 3.0 V incurs the slower tOD2 delay instead of tOD1 - design timing margins accordingly if you operate VCCIO at 2.5 V.
The 100-pin TQFP package has multiple VCCINT (pins 9, 48, 80) and VCCIO (pins 32, 64, 96) pads that must each be decoupled separately - do not share a single decoupling capacitor across pins. Route JTAG signals (TDI/TDO/TMS/TCK) as a short daisy chain with 33 ohm series termination if the cable to the programming header exceeds 50 mm; floating TMS at power-up can place the TAP controller in an undefined state and block ISP. Keep the JTAG header within 100 mm of the CPLD to avoid signal-integrity issues with the long TCK rise time.
When using the EPM7128AETC100-5N as a 5V-to-3.3V level shifter with VCCIO at 3.3 V, the inputs are 5V tolerant but the outputs swing only to 3.3 V - confirm that all downstream receivers meet VIH at 3.3 V CMOS levels (typically 2.0 V minimum). For high-speed (>50 MHz) outputs add 22-33 ohm series damping resistors to control ringing on long PCB traces; the CPLD output edge rates are sub-2 ns and will otherwise over-shoot on unterminated lines. Avoid using the same I/O bank for both 3.3 V and 2.5 V signalling because the bank VCCIO sets the drive level for the entire bank.
Informações de conformidade
RoHS compliance is implied by the "N" suffix in the part number, per Altera/Intel legacy datasheet naming. AEC-Q100 is not applicable as this is a commercial-grade CPLD; an industrial-grade version is not catalogued. REACH compliance assumed by major distributors (Heisener, DigiKey) but not explicitly stated on the datasheet excerpts provided.