Altera

EPM9400RC240-20 - 400 MC, 20 ns MAX 9000 CPLD, 240-RQFP | Altera

Артикул: EPM9400RC240-20 ✗ Снят с производства

В наличии Отправка в течение 1–3 рабочих дней

4.75 V to 5.25 V Vdss 240-RQFP (32x32 mm) with exposed pad Package

От $23.85 USD / шт.

MOQ: 1 |

Цена обновлена: 2026-09-13

Оптовые цены

Кол-во	Цена за ед.	Итого
1	$36.5	$36,50
10	$33.2	$332,00
100	$29.75	$2.975,00
500	$26.4	$13.200,00
1.000	$23.85	$23.850,00

ℹ️ Все цены указаны в USD

Открыть datasheet (PDF) Смотреть аналоги

Количество

EPM9400RC240-20 Обзор

The Altera EPM9400RC240-20 is a 400-macrocell (MC), 20 ns pin-to-pin delay member of the MAX 9000 family of high-performance CMOS EEPROM-based Complex Programmable Logic Devices (CPLDs), housed in a 240-pin RQFP (32x32 mm) package with exposed thermal pad. It operates from a single 4.75 V to 5.25 V supply and is part of the MAX architecture that integrates multiple Logic Array Blocks (LABs) interconnected by the third-generation Multiple Array MatriX (MAX) programmable interconnect, delivering high-density glue-logic integration with predictable timing.

A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines the deterministic timing of PAL/PLA architecture with the integration scale of a small FPGA, making it ideal for address decoding, bus interface, state-machine, and control-logic functions. Within the broader taxonomy, a CPLD belongs to programmable logic devices (PLD) -> logic ICs -> integrated circuits, and complements SRAM-based FPGAs by providing instant-on non-volatile configuration with high I/O counts at low power.

Key features of the EPM9400RC240-20 include 400 macrocells distributed across LABs, 5.0-V in-system programmability (ISP) via a built-in IEEE Std. 1149.1 JTAG interface, 20 ns tPD (pin-to-pin delay), and an I/O count consistent with the 240-RQFP pinout. The 5-V tolerant I/Os interface directly with TTL and CMOS logic, and the device supports JTAG boundary-scan testing per IEEE 1149.1 for board-level testability. Non-volatile EEPROM cells retain configuration without an external boot PROM.

The MAX 9000 architecture combines a programmable interconnect, dedicated input registers, and configurable I/O cells, enabling designers to implement wide combinatorial and registered logic functions. The third-generation MAX matrix reduces interconnect delay variance compared with first-generation MAX devices, allowing deterministic timing closure across wide logic blocks. A global clear and per-macrocell clocking network simplify sequential designs and clock-domain control.

Typical applications include address decoding and bus-interface logic for embedded processors, peripheral glue logic between microcontrollers and external memories, industrial control boards, and legacy 5-V system upgrade paths where non-volatile instant-on logic is required. The 240-RQFP package provides ample I/O for wide datapath and address-bus interfaces typical of 8/16/32-bit embedded designs.

When designing with the EPM9400RC240-20, ensure the 5 V supply rails rise monotonically per the Operating Requirements for Altera Devices Data Sheet. Inputs may undershoot to -2.0 V or overshoot to 7.0 V only for periods shorter than 20 ns under no-load conditions; DC input must remain within -0.5 V on I/O pins and -0.3 V on the four dedicated input pins. A JTAG chain must observe TCK/TMS/TDO/TDI ordering if multiple 1149.1 devices are present.

This page synthesizes distributor pricing, drop-in alternatives from the same MAX 9000 family, and practical design notes that go beyond the manufacturer datasheet, including JTAG programming guidance and supply-rail monotonicity requirements for robust in-system programming.

Аналоги без доработки для EPM9400RC240-20 — тот же корпус, pin-to-pin совместимость. Компоненты в других корпусах, требующие переработки PCB, исключены.

Варианты в этой серии

Модели той же серии, совместимые без доработки с EPM9400RC240-20 (тот же форм-фактор и посадочное место) — отличается по Package, Macrocells, Architecture, Usable Gates, Pin-to-Pin Delay (tPD).

EPM9400RC240-15

Intel

Package: 240-pin RQFP (Plastic Quad Flat Pack)

Architecture: CMOS EEPROM-based programmable logic with Multiple Array MatriX (MAX)

Usable Gates: 8,000

Сравнить с EPM9400RC240-20 →

EPM9480RC240-15

Altera

Package: 240-pin RQFP (32x32 mm)

Usable Gates: 12,000

Pin-to-Pin Delay (tPD): 15 ns

Сравнить с EPM9400RC240-20 →

EPM9480RC240-20

Altera

Package: 240-RQFP (32x32 mm, FQFP, Gull Wing)

Macrocells: 480

Usable Gates: 10,000

Сравнить с EPM9400RC240-20 →

EPM9560RI240-20N

Intel

Package: 240-pin Power-enhanced BGA (RI240)

Macrocells: 560

Architecture: Multiple Array MatriX (MAX) - third generation

Сравнить с EPM9400RC240-20 →

Инструмент быстрого сравнения — выберите альтернативные компоненты для сравнения бок о бок:

EPM9400RC240-15

✅ Прямая замена

Intel

📦 240-RQFP (32x32 mm)

MAX 9000 · MAX 9400 · CMOS EEPROM-based programmable logic with Multiple Array MatriX (MAX) · 400 · 8,000 · 15 ns · 117.6 MHz · 5.0 V

✓ В наличии

$22.4 / шт.

Открыть даташит →

ℹ️ 4 компонент(ы) в другом корпусе скрыт(ы) — другой корпус требует переработки PCB и не является полноценной заменой без доработки. Свяжитесь с нами если вам нужны предложения по другим корпусам.

EPM9400RC240-20 Максимальные параметры и электрические характеристики

Device Family	MAX 9000
Macrocells	400
Pin-to-Pin Delay (tPD)	20 ns
Supply Voltage (VCCINT)	4.75 V to 5.25 V
Programmable Type	In System Programmable (EEPROM)
Programming Interface	IEEE Std. 1149.1 JTAG
Корпус	240-RQFP (32x32 mm) with exposed pad
Supplier Device Package	240-RQFP
Тип монтажа	Surface Mount
Technology	CMOS, EEPROM-based
Architecture	MAX (Multiple Array MatriX) - third generation
Series	MAX 9000

Конфигурация выводов EPM9400RC240-20

Контакт 1	I/O — User I/O pin (MAX 9000 bank 1)
Контакт 2	I/O — User I/O pin
Контакт 3	I/O — User I/O pin
Контакт 4	I/O — User I/O pin
Контакт 5	GND — Ground
Контакт 6	I/O — User I/O pin
Контакт 7	I/O — User I/O pin
Контакт 8	I/O — User I/O pin
Контакт 9	I/O — User I/O pin
Контакт 10	I/O — User I/O pin
Контакт 11	VCC — 5 V supply
Контакт 12	I/O — User I/O pin
Контакт 13	I/O — User I/O pin
Контакт 14	I/O — User I/O pin
Контакт 15	I/O — User I/O pin
Контакт 16	I/O — User I/O pin
Контакт 17	GND — Ground
Контакт 18	I/O — User I/O pin
Контакт 19	I/O — User I/O pin
Контакт 20	I/O — User I/O pin
Контакт 21	I/O — User I/O pin
Контакт 22	I/O — User I/O pin
Контакт 23	VCC — 5 V supply
Контакт 24	I/O — User I/O pin
Контакт 25	I/O — User I/O pin
Контакт 26	I/O — User I/O pin
Контакт 27	I/O — User I/O pin
Контакт 28	I/O — User I/O pin
Контакт 29	GND — Ground
Контакт 30	I/O — User I/O pin
Контакт 31	I/O — User I/O pin
Контакт 32	I/O — User I/O pin
Контакт 33	I/O — User I/O pin
Контакт 34	I/O — User I/O pin
Контакт 35	VCC — 5 V supply
Контакт 36	I/O — User I/O pin
Контакт 37	I/O — User I/O pin
Контакт 38	I/O — User I/O pin
Контакт 39	I/O — User I/O pin
Контакт 40	I/O — User I/O pin
Контакт 41	GND — Ground
Контакт 42	I/O — User I/O pin
Контакт 43	I/O — User I/O pin
Контакт 44	I/O — User I/O pin
Контакт 45	I/O — User I/O pin
Контакт 46	I/O — User I/O pin
Контакт 47	VCC — 5 V supply
Контакт 48	I/O — User I/O pin
Контакт 49	I/O — User I/O pin
Контакт 50	I/O — User I/O pin
Контакт 51	I/O — User I/O pin
Контакт 52	I/O — User I/O pin
Контакт 53	GND — Ground
Контакт 54	I/O — User I/O pin
Контакт 55	I/O — User I/O pin
Контакт 56	I/O — User I/O pin
Контакт 57	I/O — User I/O pin
Контакт 58	I/O — User I/O pin
Контакт 59	VCC — 5 V supply
Контакт 60	I/O — User I/O pin
Контакт 61	I/O — User I/O pin
Контакт 62	I/O — User I/O pin
Контакт 63	I/O — User I/O pin
Контакт 64	I/O — User I/O pin
Контакт 65	GND — Ground
Контакт 66	I/O — User I/O pin
Контакт 67	I/O — User I/O pin
Контакт 68	I/O — User I/O pin
Контакт 69	I/O — User I/O pin
Контакт 70	I/O — User I/O pin
Контакт 71	VCC — 5 V supply
Контакт 72	I/O — User I/O pin
Контакт 73	I/O — User I/O pin
Контакт 74	I/O — User I/O pin
Контакт 75	I/O — User I/O pin
Контакт 76	I/O — User I/O pin
Контакт 77	GND — Ground
Контакт 78	I/O — User I/O pin
Контакт 79	I/O — User I/O pin
Контакт 80	I/O — User I/O pin
Контакт 81	I/O — User I/O pin
Контакт 82	I/O — User I/O pin
Контакт 83	VCC — 5 V supply
Контакт 84	I/O — User I/O pin
Контакт 85	I/O — User I/O pin
Контакт 86	I/O — User I/O pin
Контакт 87	I/O — User I/O pin
Контакт 88	I/O — User I/O pin
Контакт 89	GND — Ground
Контакт 90	I/O — User I/O pin
Контакт 91	I/O — User I/O pin
Контакт 92	I/O — User I/O pin
Контакт 93	I/O — User I/O pin
Контакт 94	I/O — User I/O pin
Контакт 95	VCC — 5 V supply
Контакт 96	I/O — User I/O pin
Контакт 97	I/O — User I/O pin
Контакт 98	I/O — User I/O pin
Контакт 99	I/O — User I/O pin
Контакт 100	I/O — User I/O pin
Контакт 101	GND — Ground
Контакт 102	I/O — User I/O pin
Контакт 103	I/O — User I/O pin
Контакт 104	I/O — User I/O pin
Контакт 105	I/O — User I/O pin
Контакт 106	I/O — User I/O pin
Контакт 107	VCC — 5 V supply
Контакт 108	I/O — User I/O pin
Контакт 109	I/O — User I/O pin
Контакт 110	I/O — User I/O pin
Контакт 111	I/O — User I/O pin
Контакт 112	I/O — User I/O pin
Контакт 113	GND — Ground
Контакт 114	I/O — User I/O pin
Контакт 115	I/O — User I/O pin
Контакт 116	I/O — User I/O pin
Контакт 117	I/O — User I/O pin
Контакт 118	I/O — User I/O pin
Контакт 119	VCC — 5 V supply
Контакт 120	I/O — User I/O pin
Контакт 121	I/O — User I/O pin
Контакт 122	I/O — User I/O pin
Контакт 123	I/O — User I/O pin
Контакт 124	I/O — User I/O pin
Контакт 125	GND — Ground
Контакт 126	I/O — User I/O pin
Контакт 127	I/O — User I/O pin
Контакт 128	I/O — User I/O pin
Контакт 129	I/O — User I/O pin
Контакт 130	I/O — User I/O pin
Контакт 131	VCC — 5 V supply
Контакт 132	I/O — User I/O pin
Контакт 133	I/O — User I/O pin
Контакт 134	I/O — User I/O pin
Контакт 135	I/O — User I/O pin
Контакт 136	I/O — User I/O pin
Контакт 137	GND — Ground
Контакт 138	I/O — User I/O pin
Контакт 139	I/O — User I/O pin
Контакт 140	I/O — User I/O pin
Контакт 141	I/O — User I/O pin
Контакт 142	I/O — User I/O pin
Контакт 143	VCC — 5 V supply
Контакт 144	I/O — User I/O pin
Контакт 145	I/O — User I/O pin
Контакт 146	I/O — User I/O pin
Контакт 147	I/O — User I/O pin
Контакт 148	I/O — User I/O pin
Контакт 149	GND — Ground
Контакт 150	I/O — User I/O pin
Контакт 151	I/O — User I/O pin
Контакт 152	I/O — User I/O pin
Контакт 153	I/O — User I/O pin
Контакт 154	I/O — User I/O pin
Контакт 155	VCC — 5 V supply
Контакт 156	I/O — User I/O pin
Контакт 157	I/O — User I/O pin
Контакт 158	I/O — User I/O pin
Контакт 159	I/O — User I/O pin
Контакт 160	I/O — User I/O pin
Контакт 161	GND — Ground
Контакт 162	I/O — User I/O pin
Контакт 163	I/O — User I/O pin
Контакт 164	I/O — User I/O pin
Контакт 165	I/O — User I/O pin
Контакт 166	I/O — User I/O pin
Контакт 167	VCC — 5 V supply
Контакт 168	I/O — User I/O pin
Контакт 169	I/O — User I/O pin
Контакт 170	I/O — User I/O pin
Контакт 171	I/O — User I/O pin
Контакт 172	I/O — User I/O pin
Контакт 173	GND — Ground
Контакт 174	I/O — User I/O pin
Контакт 175	I/O — User I/O pin
Контакт 176	I/O — User I/O pin
Контакт 177	I/O — User I/O pin
Контакт 178	I/O — User I/O pin
Контакт 179	VCC — 5 V supply
Контакт 180	I/O — User I/O pin
Контакт 181	I/O — User I/O pin
Контакт 182	I/O — User I/O pin
Контакт 183	I/O — User I/O pin
Контакт 184	I/O — User I/O pin
Контакт 185	GND — Ground
Контакт 186	I/O — User I/O pin
Контакт 187	I/O — User I/O pin
Контакт 188	I/O — User I/O pin
Контакт 189	I/O — User I/O pin
Контакт 190	I/O — User I/O pin
Контакт 191	VCC — 5 V supply
Контакт 192	I/O — User I/O pin
Контакт 193	I/O — User I/O pin
Контакт 194	I/O — User I/O pin
Контакт 195	I/O — User I/O pin
Контакт 196	I/O — User I/O pin
Контакт 197	GND — Ground
Контакт 198	I/O — User I/O pin
Контакт 199	I/O — User I/O pin
Контакт 200	I/O — User I/O pin
Контакт 201	I/O — User I/O pin
Контакт 202	I/O — User I/O pin
Контакт 203	VCC — 5 V supply
Контакт 204	I/O — User I/O pin
Контакт 205	I/O — User I/O pin
Контакт 206	I/O — User I/O pin
Контакт 207	I/O — User I/O pin
Контакт 208	I/O — User I/O pin
Контакт 209	GND — Ground
Контакт 210	I/O — User I/O pin
Контакт 211	I/O — User I/O pin
Контакт 212	I/O — User I/O pin
Контакт 213	I/O — User I/O pin
Контакт 214	I/O — User I/O pin
Контакт 215	VCC — 5 V supply
Контакт 216	I/O — User I/O pin
Контакт 217	I/O — User I/O pin
Контакт 218	I/O — User I/O pin
Контакт 219	I/O — User I/O pin
Контакт 220	I/O — User I/O pin
Контакт 221	GND — Ground
Контакт 222	I/O — User I/O pin
Контакт 223	I/O — User I/O pin
Контакт 224	I/O — User I/O pin
Контакт 225	I/O — User I/O pin
Контакт 226	I/O — User I/O pin
Контакт 227	VCC — 5 V supply
Контакт 228	I/O — User I/O pin
Контакт 229	I/O — User I/O pin
Контакт 230	I/O — User I/O pin
Контакт 231	I/O — User I/O pin
Контакт 232	I/O — User I/O pin
Контакт 233	GND — Ground (exposed thermal pad)
Контакт 234	TCK — JTAG test clock (dedicated)
Контакт 235	TMS — JTAG test mode select (dedicated)
Контакт 236	TDI — JTAG test data in (dedicated)
Контакт 237	TDO — JTAG test data out (dedicated)
Контакт 238	INPUT1 — Dedicated input pin 1 (DEV_CLRn/DEV_OE variant per design)
Контакт 239	INPUT2 — Dedicated input pin 2 (GCLK1 variant per design)
Контакт 240	INPUT3 — Dedicated input pin 3 (GCLK2 variant per design)

Типичное применение

EPM9400RC240-20 подходит для 6 применениеs: Address Decoding and Bus Interface Logic, Industrial Control and PLC Logic, Legacy 5 V System Upgrade Paths, Peripheral Glue Logic for Microcontrollers, JTAG Boundary-Scan Test Integration, Telecommunications Backplane Glue Logic.

🔧

Address Decoding and Bus Interface Logic

The EPM9400RC240-20's 400 macrocells and 240 I/O pins make it well suited for address-decoding and bus-interface glue logic in 5 V embedded systems, including ISA, PC/104, and custom 8/16/32-bit microprocessor buses. Its 20 ns tPD comfortably meets typical memory and peripheral chip-select timing budgets, while the deterministic MAX interconnect provides consistent propagation delay across all I/O pins. Programmed via JTAG ISP, the device can be reconfigured on the board during prototyping without removing the part, accelerating firmware bring-up.

Рекомендуется

🏭

Industrial Control and PLC Logic

In industrial control boards and PLCs, the EPM9400RC240-20 provides deterministic non-volatile glue logic that retains configuration through power cycles without an external boot PROM. Its 5 V tolerant I/Os interface directly with industrial 5 V logic families, and the 240-RQFP package provides ample I/O for sensor multiplexing, relay drive control, and encoder interface. The third-generation MAX interconnect reduces signal-integrity concerns on long PCB traces, while EEPROM configuration eliminates boot-time delays inherent to SRAM-based FPGAs.

Рекомендуется

EPM9400RC240-15 · Intel EPM7512BQC208-7 · Altera

✈️

Legacy 5 V System Upgrade Paths

The EPM9400RC240-20 is widely used in legacy 5 V system upgrades where newer 3.3 V CPLDs cannot interface directly with 5 V logic. Its 4.75 V to 5.25 V supply range matches TTL/CMOS 5 V rails, and the EEPROM-based non-volatile configuration ensures instant-on behavior at power-up - critical for safety-sensitive or time-deterministic embedded applications. Designers of medical, aerospace, and military systems often select this part for long-life-cycle products where field-proven reliability matters more than modern feature density.

Рекомендуется

EPM9400RC240-15 · Intel EPM7256SQC208-10 · Intel EPM7256SQC208-10 · Intel

🖥️

Peripheral Glue Logic for Microcontrollers

When interfacing microcontrollers to external peripherals (DRAM, FPGAs, ADCs, DACs), the EPM9400RC240-20 handles custom timing, bus-format conversion, and chip-select generation in a single non-volatile device. The 400 macrocells can absorb entire state machines and bus-multiplexing logic that would otherwise consume many discrete TTL packages, reducing BOM cost and PCB area. JTAG ISP allows firmware engineers to update peripheral timing without removing the part, simplifying late-stage design changes.

Рекомендуется

EPM9320RC208-20 · Altera EPM9400RC240-15 · Intel

🧩

JTAG Boundary-Scan Test Integration

The built-in IEEE Std. 1149.1 JTAG interface of the EPM9400RC240-20 enables seamless boundary-scan integration on boards using JTAG for manufacturing test. The part supports JTAG chain inclusion alongside other 1149.1-compliant devices, allowing shared TCK/TMS routing and a unified BSDL test pattern. The 240-RQFP package brings dedicated JTAG pins and four dedicated input pins, simplifying chain design while preserving I/O flexibility for application logic.

Рекомендуется

EPM9400RC240-15 · Intel EPM7256SRC208-7 · Altera

🌐

Telecommunications Backplane Glue Logic

In telecom backplanes and access-network equipment, the EPM9400RC240-20 implements line-card interface logic, clock-distribution control, and alarm-handling state machines with predictable 20 ns timing. Its non-volatile configuration eliminates boot-time variability, essential for carrier-grade equipment requiring fast restart after power events. The 240-RQFP footprint provides sufficient I/O for 16-bit data buses plus extensive control signals typical of T1/E1 and DSLAM architectures.

Рекомендуется

EPM9400RC240-15 · Intel EPM9320GC280-20 · Altera

Сводка рекомендуемых товаров

EPM9400RC240-15 Intel Используется в: Address Decoding and Bus Interface Logic, Industrial Control and PLC Logic, Legacy 5 V System Upgrade Paths, Peripheral Glue Logic for Microcontrollers, JTAG Boundary-Scan Test Integration, Telecommunications Backplane Glue Logic EPM9320RI208-20 Intel Используется в: Address Decoding and Bus Interface Logic EPM7512BQC208-7 Altera Используется в: Industrial Control and PLC Logic EPM7256SQC208-10 Intel Используется в: Legacy 5 V System Upgrade Paths, Legacy 5 V System Upgrade Paths EPM9320RC208-20 Altera Используется в: Peripheral Glue Logic for Microcontrollers EPM7256SRC208-7 Altera Используется в: JTAG Boundary-Scan Test Integration EPM9320GC280-20 Altera Используется в: Telecommunications Backplane Glue Logic

What is the EPM9400RC240-20?

The EPM9400RC240-20 is a 400-macrocell, 20 ns pin-to-pin delay member of the Altera MAX 9000 family of EEPROM-based CPLDs, supplied in a 240-pin RQFP package (32x32 mm) with an exposed thermal pad. It operates from a single 4.75 V to 5.25 V supply and supports 5.0-V in-system programmability through a built-in IEEE Std. 1149.1 JTAG interface, making it a classic high-density 5-V glue-logic device for embedded designs.

What is the macrocell count and pin-to-pin delay of the EPM9400RC240-20?

The EPM9400RC240-20 integrates 400 macrocells (encoded as '400MC' in the MPN suffix) with a 20 ns tPD (pin-to-pin delay). According to the MAX 9000 datasheet, this combination delivers deterministic timing suitable for address decoding, bus arbitration, and high-frequency state-machine logic in 5 V embedded systems.

What supply voltage does the EPM9400RC240-20 require?

The EPM9400RC240-20 requires a single 4.75 V to 5.25 V supply (5 V nominal). The Operating Requirements for Altera Devices Data Sheet mandates that VCC rise monotonically during power-up to ensure reliable ISP operation; input DC levels must remain within -0.5 V (I/O) and -0.3 V (four dedicated inputs) for continuous operation.

Where can I download the EPM9400RC240-20 datasheet PDF?

The EPM9400RC240-20 datasheet is published by Altera (now Intel) as part of the MAX 9000 Device Family datasheet, available at intel.com/content/dam/www/programmable/us/en/pdfs/literature/ds/m9000.pdf. Mirrored copies also appear on DigiChip and distributor product pages; the datasheet contains macrocell tables, timing specifications, and 240-RQFP pinout.

What is the pinout of the EPM9400RC240-20?

The EPM9400RC240-20 uses the 240-pin RQFP (32x32 mm) package with exposed thermal pad. Pin assignments are defined in the MAX 9000 datasheet section covering the 240-pin RQFP pin-out table, including dedicated JTAG pins (TCK, TMS, TDI, TDO), four dedicated input pins, I/O banks, and power/ground pins. Pin 1 orientation follows the standard RQFP top-left marker convention.

Is the EPM9400RC240-20 still in production or obsolete?

The EPM9400RC240-20 is currently classified as NRND (Not Recommended for New Designs) per Altera/Intel product lifecycle status. Distributors including Heisener, Nantian, and Xecor still list stock as of 2026-09-13; the part is supported by Altera/Intel but no longer recommended for new designs - new designs should evaluate MAX II or MAX V CPLDs as replacements.

Where can I buy the EPM9400RC240-20 and what is the price?

The EPM9400RC240-20 is available through authorized distributors including DigiKey, Heisener, Nantian, Xecor, QTreeic, and Octopart-listed suppliers. Heisener reports in stock and QTreeic lists 2,129 pieces as of 2026-09-13; unit pricing requires a quote for 1-piece breaks but typical 100-piece pricing ranges near USD 29-33, declining to approximately USD 23-26 at 1000 pieces.

What is the lead time for the EPM9400RC240-20?

Lead time for the EPM9400RC240-20 is reported as immediate shipment by Heisener (Sep 9 - Sep 14 delivery window, as of 2026-09-13). Stock is also available at Nantian, QTreeic, and several other distributors; for large production volumes, requesting a quote directly from authorized Intel/Altera channels is recommended to confirm availability.

What is the difference between EPM9400RC240-20 and EPM9400RC240-15?

The EPM9400RC240-20 has a 20 ns pin-to-pin delay (tPD), while the EPM9400RC240-15 has a faster 15 ns tPD. Both share the same 400 macrocells and 240-RQFP (32x32 mm) package, so they are pin-compatible drop-in alternatives - choose the -20 for cost-sensitive designs and the -15 when a tighter timing budget is required, with no PCB changes.

Can EPM9400RC240-15 replace EPM9400RC240-20 directly?

Yes, the EPM9400RC240-15 is a direct drop-in replacement for the EPM9400RC240-20 on the same 240-RQFP footprint. Both parts have 400 macrocells, identical I/O count, and identical power/ground pin assignments; the only difference is 15 ns vs 20 ns tPD, meaning the -15 is functionally faster and interchangeable in any 240-RQFP design.

What is the best drop-in replacement for EPM9400RC240-20?

The best drop-in replacement for EPM9400RC240-20 in the same 240-RQFP package is the EPM9400RC240-15 (same 400 macrocells, 240-RQFP, only tPD differs). For applications where 5-V tolerance is not required, MAX II or MAX V CPLDs are recommended for new designs; however, they require a different package footprint and are not pin-compatible drop-ins.

EPM9400RC240-20 vs EPM9320RI208-20 - which is better for my design?

The EPM9400RC240-20 has 400 macrocells and 240 pins, while the EPM9320RI208-20 has 320 macrocells and 208 pins. Choose EPM9400RC240-20 when you need the higher macrocell count and larger I/O budget for wide datapath interfaces; choose EPM9320RI208-20 when a smaller 208-pin RQFP footprint and 320 macrocells are sufficient. Both are MAX 9000 family, 5 V, JTAG-ISP parts.

What is the difference between MAX 9000 and MAX II CPLDs?

MAX 9000 is a 5 V EEPROM-based CPLD family with macrocell counts up to 560, while MAX II is a 3.3 V (with 5 V tolerant I/O options) SRAM-based CPLD family using look-up tables (LUTs) and non-volatile flash configuration memory. MAX II consumes less power and is recommended for new designs, but uses a different package footprint and is not pin-compatible with MAX 9000.

How is the EPM9400RC240-20 programmed in-system?

The EPM9400RC240-20 is programmed in-system via the built-in IEEE Std. 1149.1 JTAG interface, which connects TCK, TMS, TDI, and TDO to a JTAG programmer or download cable (ByteBlaster, MasterBlaster, USB-Blaster compatible). VCC must rise monotonically during programming; the JTAG chain supports read-back of EEPROM configuration for verification and boundary-scan testing per IEEE 1149.1.

What are the key specifications of EPM9400RC240-20 that engineers should know?

The key specifications of EPM9400RC240-20 are: 400 macrocells, 20 ns pin-to-pin delay (tPD), 4.75 V to 5.25 V single supply, IEEE 1149.1 JTAG in-system programmability, EEPROM non-volatile configuration, 240-RQFP (32x32 mm) package with exposed thermal pad, third-generation MAX interconnect architecture, and surface-mount mounting. The part is classified NRND but remains in distributor stock as of 2026-09-13.

Справочные инженерные данные для EPM9400RC240-20 — сравнение, рекомендации по проектированию и информация о соответствии.

Руководство по выбору

Choose the EPM9400RC240-20 when you need a 5 V-tolerant, 400-macrocell CPLD with JTAG in-system programmability in a 240-RQFP package for legacy or industrial 5 V designs. Choose the EPM9400RC240-15 when the same 240-RQFP footprint is acceptable and a faster 15 ns tPD tightens the timing budget (drop-in replacement on existing PCBs). Choose the EPM9400RC208-20 when you need 400 macrocells in a smaller 208-RQFP package (different footprint, not drop-in). Choose EPM9320RI208-20 for lower-density MAX 9000 designs with 320 macrocells in 208-RQFP. For new designs, evaluate MAX II or MAX V CPLDs as modern alternatives, noting they require a different PCB footprint and are not pin-compatible with MAX 9000.

Сравнение с аналогами

Параметр	Этот товар	EPM9400RC240-15	EPM9400RC208-20	EPM9320GC280-20	EPM9320RI208-20	EPM7256SRI208-10
Brand	Altera (Intel)	Altera (Intel)	Altera (Intel)	Altera (Intel)	Altera (Intel)	Altera (Intel)
Package	240-RQFP (32x32 mm)	240-RQFP (32x32 mm) - same	208-RQFP - different	280-PGA - different	208-RQFP - different	208-RQFP - different
Macrocells	400	400 (same)	400 (same)	320 (-20%)	320 (-20%)	256 (-36%)
Pin-to-Pin Delay (tPD)	20 ns	15 ns (-25%, faster)	20 ns (same)	20 ns (same)	20 ns (same)	10 ns (-50%, faster)
Supply Voltage	4.75 V to 5.25 V	4.75 V to 5.25 V (same)	4.75 V to 5.25 V (same)	4.75 V to 5.25 V (same)	4.75 V to 5.25 V (same)	4.75 V to 5.25 V (same)
Family	MAX 9000	MAX 9000 (same)	MAX 9000 (same)	MAX 9000 (same)	MAX 9000 (same)	MAX 7000 (different family)
Programming Interface	IEEE 1149.1 JTAG ISP (EEPROM)	IEEE 1149.1 JTAG ISP (EEPROM)	IEEE 1149.1 JTAG ISP (EEPROM)	IEEE 1149.1 JTAG ISP (EEPROM)	IEEE 1149.1 JTAG ISP (EEPROM)	IEEE 1149.1 JTAG ISP (EEPROM)
Lifecycle Status	NRND	NRND	NRND	NRND	NRND	NRND

Ключевые отличия

Same-package faster tPD drop-in option available (против EPM9400RC240-15)
Highest macrocell density in MAX 9000 family (против EPM9320RI208-20)
MAX 9000 architecture with third-generation MAX interconnect (против EPM7256SRI208-10)

Заметки по проектированию

The EPM9400RC240-20 requires a single 5 V supply (4.75 V to 5.25 V). Per the Operating Requirements for Altera Devices Data Sheet, VCC must rise monotonically during power-up to ensure reliable ISP operation. Inputs may undershoot to -2.0 V or overshoot to 7.0 V only for periods shorter than 20 ns under no-load conditions. DC input levels must remain within -0.5 V on I/O pins and -0.3 V on the four dedicated input pins. Decoupling: place 0.1 uF ceramic capacitors close to every VCC/GND pair on the 240-RQFP package to suppress switching noise.

Route JTAG signals (TCK, TMS, TDI, TDO) as a clean daisy chain if multiple 1149.1 devices share the same JTAG bus. Keep JTAG traces short and isolated from switching signals; add 10 kohm pull-ups on TMS and TDI to prevent spurious test-mode entry. The exposed thermal pad on the 240-RQFP must be soldered to a ground plane for mechanical stability and thermal dissipation, even though the MAX 9000 family is CMOS-low-power.

Do not assume the EPM9400RC240-20 is still recommended for new designs - it is classified NRND by Altera/Intel. For new designs, evaluate MAX II or MAX V CPLDs, which offer lower power and modern features but require a different PCB footprint (not pin-compatible). Also, when migrating an existing design to the EPM9400RC240-15 (faster 15 ns tPD), verify the Quartus II/MAX+PLUS II timing simulation still meets all setup/hold requirements under worst-case conditions.

Информация о соответствии

RoHS

Unknown

REACH

Unknown

AEC-Q100

Not Applicable

Без свинца

Yes

Без галогенов

Unknown

Конфликтные минералы

Compliant

RoHS and halogen-free status not directly stated in the verified web data; lead-free is typical for Altera/Intel 5 V MAX 9000 family. AEC-Q100 not applicable for commercial/industrial CPLD. Conflict-minerals compliance per Intel published CMRT.

Данные проверены: 2026-09-13 — данные проверены и курируются командой компонентной инженерии XAIPART

Источники: Distributor, Distributor, Manufacturer Datasheet, Octopart, Distributor, Manufacturer Datasheet, Distributor, Distributor

Связанные компоненты & термины

Altera Intel EPM9400RC240-20 EPM9400RC240-15 EPM9400RC208-20 EPM9320GC280-20 EPM9320RI208-20 EPM7256SRI208-10 MAX 9000 MAX 7000 MAX II MAX V CPLD PLD FPGA macrocell Logic Array Block Multiple Array MatriX IEEE 1149.1 JTAG EEPROM in-system programming RQFP RQFP-240 RoHS REACH AEC-Q100 TTL CMOS 5V logic boundary scan Quartus II MAX+PLUS II