EPM9320RC208-20 - 320-Macrocell MAX 9000 CPLD, 20ns | Altera
Артикул: EPM9320RC208-20 ✗ Снят с производства| Кол-во | Цена за ед. | Итого |
|---|---|---|
| 1 | $38.5 | $38,50 |
| 10 | $34.2 | $342,00 |
| 100 | $29.8 | $2.980,00 |
| 500 | $25.4 | $12.700,00 |
| 1.000 | $21.9 | $21.900,00 |
EPM9320RC208-20 Обзор
A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL-like macrocell blocks with a programmable interconnect matrix, sitting in the programmable logic hierarchy between simple SPLDs/GALs and higher-density FPGAs. CPLDs are favored for glue-logic, bus-interface, state-machine, and power-on control tasks where deterministic timing, fast input-to-output response, and instant-on (zero-config-time) operation are required. The MAX 9000 family extends this concept to higher densities than earlier MAX 5000/7000 generations while retaining the predictable timing that makes CPLDs the preferred choice for asynchronous logic replacement.
Key features of the EPM9320RC208-20 include 320 macrocells organized across 20 logic array blocks (LABs), 132 user I/O pins, 5.0 V in-system programmability through the JTAG-compliant IEEE 1149.1 boundary-scan interface, and a commercial 0 °C to 70 °C operating-temperature range. The exposed-pad RQFP-208 package provides a thermal path for moderate dissipation in surface-mount designs, and the EEPROM process allows unlimited reprogramming cycles without an external configuration memory. The device operates from a single 4.75 V to 5.25 V supply, simplifying integration into legacy 5 V logic systems.
Architecturally, the MAX 9000 device combines high-density AND-OR PLA-style logic with fast, deterministic interconnect, giving every macrocell a fixed, predictable delay independent of the design's routing complexity. This contrasts sharply with SRAM-based FPGAs, whose interconnect delays vary with placement. The 132 available I/O pins are 5 V-tolerant within the supply range, supporting TTL and CMOS interfacing without level shifters, and each pin is JTAG-controlled for boundary-scan testability.
Typical applications for the EPM9320RC208-20 include 5 V glue-logic consolidation in industrial controllers, address decoding and bus-interface bridging in legacy microprocessor systems, peripheral control logic in telecommunications and networking equipment, and state-machine replacement in instrumentation. Its instant-on non-volatile behavior makes it especially suitable for safety-critical boot logic that must be valid before any host processor runs.
When designing with this part, observe the 4.75 V to 5.25 V supply window and keep all inputs within the absolute maximum ratings specified in the datasheet; the exposed thermal pad must be soldered to a sufficient copper area to keep junction temperature within the commercial 0 °C to 70 °C range. Use Altera's MAX+PLUS II or Quartus II legacy support tools to fit designs, and verify JTAG chain order when multiple devices share the same boundary-scan port.
This page synthesizes distributor pricing, same-package drop-in alternatives, and practical 5 V glue-logic design notes for the EPM9320RC208-20 - information not consolidated in the Altera datasheet alone.
Аналоги без доработки для EPM9320RC208-20 — тот же корпус, pin-to-pin совместимость. Компоненты в других корпусах, требующие переработки PCB, исключены.
Варианты в этой серии
Модели той же серии, совместимые без доработки с EPM9320RC208-20 (тот же форм-фактор и посадочное место) — отличается по Package, In-System Programmability, Operating Temperature, Usable Gates, Configuration Memory.
Инструмент быстрого сравнения — выберите альтернативные компоненты для сравнения бок о бок:
EPM9320RC208-15
✅ Прямая замена✓ В наличии
Уточнить цену
Открыть даташит →EPM9320RC208-15N
✅ Прямая замена✓ В наличии
Уточнить цену
Открыть даташит →EPM9320RC208-10
✅ Прямая замена✓ В наличии
$26.4 / шт.
Открыть даташит →EPM9320ARC208-10
✅ Прямая замена✓ В наличии
$21.4 / шт.
Открыть даташит →EPM9320ARC208-10N
✅ Прямая замена✓ В наличии
$19.45 / шт.
Открыть даташит →EPM9320GC280-20
✅ Прямая замена✓ В наличии
$67 / шт.
Открыть даташит →EPM9320ARI208-10
✅ Прямая замена✓ В наличии
$27.2 / шт.
Открыть даташит →EPM9320RC208-20 Максимальные параметры и электрические характеристики
| Family | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Macrocells | 320 |
| Logic Array Blocks (LABs) | 20 |
| Usable Gates | 6,000 |
| Maximum I/O Pins | 132 |
| Propagation Delay (tPD max) | 20 ns |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V |
| Programming Technology | EEPROM, in-system programmable (ISP) |
| Boundary-Scan Interface | IEEE Std. 1149.1 (JTAG) |
| Рабочая температура | 0 °C to 70 °C (commercial) |
| Корпус | 208-RQFP, exposed pad (208-BFQFP) |
| Тип монтажа | Surface Mount |
| Architecture | Multiple Array Matrix (MAX), 3rd generation |
| Process Technology | CMOS, 5.0 V EEPROM |
| Reprogrammability | Yes, unlimited ISP cycles |
Конфигурация выводов EPM9320RC208-20
| Контакт 1 | I/O — User I/O pin (pin 1 of 208-RQFP) |
| Контакт 2 | I/O — User I/O pin |
| Контакт 3 | I/O — User I/O pin |
| Контакт 4 | I/O — User I/O pin |
| Контакт 5 | I/O — User I/O pin |
| Контакт 6 | GND — Ground |
| Контакт 7 | I/O — User I/O pin |
| Контакт 8 | I/O — User I/O pin |
| Контакт 9 | I/O — User I/O pin |
| Контакт 10 | I/O — User I/O pin |
| Контакт 11 | I/O — User I/O pin |
| Контакт 12 | VCC — 5.0 V supply (VCCINT) |
| Контакт 13 | I/O — User I/O pin |
| Контакт 14 | I/O — User I/O pin |
| Контакт 15 | I/O — User I/O pin |
| Контакт 16 | I/O — User I/O pin |
| Контакт 17 | I/O — User I/O pin |
| Контакт 18 | I/O — User I/O pin |
| Контакт 19 | GND — Ground |
| Контакт 20 | I/O — User I/O pin |
| Контакт 21 | I/O — User I/O pin |
| Контакт 22 | I/O — User I/O pin |
| Контакт 23 | I/O — User I/O pin |
| Контакт 24 | I/O — User I/O pin |
| Контакт 25 | TDI — JTAG Test Data In (IEEE 1149.1) |
| Контакт 26 | TMS — JTAG Test Mode Select |
| Контакт 27 | TCK — JTAG Test Clock |
| Контакт 28 | VCC — 5.0 V supply |
| Контакт 29 | I/O — User I/O pin |
| Контакт 30 | I/O — User I/O pin |
| Контакт 31 | I/O — User I/O pin |
| Контакт 32 | I/O — User I/O pin |
| Контакт 33 | I/O — User I/O pin |
| Контакт 34 | GND — Ground |
| Контакт 35 | I/O — User I/O pin |
| Контакт 36 | I/O — User I/O pin |
| Контакт 37 | I/O — User I/O pin |
| Контакт 38 | I/O — User I/O pin |
| Контакт 39 | I/O — User I/O pin |
| Контакт 40 | I/O — User I/O pin |
| Контакт 41 | I/O — User I/O pin |
| Контакт 42 | VCC — 5.0 V supply |
| Контакт 43 | I/O — User I/O pin |
| Контакт 44 | I/O — User I/O pin |
| Контакт 45 | I/O — User I/O pin |
| Контакт 46 | I/O — User I/O pin |
| Контакт 47 | I/O — User I/O pin |
| Контакт 48 | I/O — User I/O pin |
| Контакт 49 | GND — Ground |
| Контакт 50 | I/O — User I/O pin |
| Контакт 51 | I/O — User I/O pin |
| Контакт 52 | I/O — User I/O pin |
| Контакт 53 | I/O — User I/O pin |
| Контакт 54 | I/O — User I/O pin |
| Контакт 55 | I/O — User I/O pin |
| Контакт 56 | I/O — User I/O pin |
| Контакт 57 | VCC — 5.0 V supply |
| Контакт 58 | I/O — User I/O pin |
| Контакт 59 | I/O — User I/O pin |
| Контакт 60 | I/O — User I/O pin |
| Контакт 61 | I/O — User I/O pin |
| Контакт 62 | I/O — User I/O pin |
| Контакт 63 | I/O — User I/O pin |
| Контакт 64 | GND — Ground |
| Контакт 65 | I/O — User I/O pin |
| Контакт 66 | I/O — User I/O pin |
| Контакт 67 | I/O — User I/O pin |
| Контакт 68 | I/O — User I/O pin |
| Контакт 69 | I/O — User I/O pin |
| Контакт 70 | I/O — User I/O pin |
| Контакт 71 | I/O — User I/O pin |
| Контакт 72 | VCC — 5.0 V supply |
| Контакт 73 | I/O — User I/O pin |
| Контакт 74 | I/O — User I/O pin |
| Контакт 75 | I/O — User I/O pin |
| Контакт 76 | I/O — User I/O pin |
| Контакт 77 | I/O — User I/O pin |
| Контакт 78 | I/O — User I/O pin |
| Контакт 79 | GND — Ground |
| Контакт 80 | I/O — User I/O pin |
| Контакт 81 | I/O — User I/O pin |
| Контакт 82 | I/O — User I/O pin |
| Контакт 83 | I/O — User I/O pin |
| Контакт 84 | I/O — User I/O pin |
| Контакт 85 | I/O — User I/O pin |
| Контакт 86 | I/O — User I/O pin |
| Контакт 87 | VCC — 5.0 V supply |
| Контакт 88 | I/O — User I/O pin |
| Контакт 89 | I/O — User I/O pin |
| Контакт 90 | I/O — User I/O pin |
| Контакт 91 | I/O — User I/O pin |
| Контакт 92 | I/O — User I/O pin |
| Контакт 93 | I/O — User I/O pin |
| Контакт 94 | GND — Ground |
| Контакт 95 | I/O — User I/O pin |
| Контакт 96 | I/O — User I/O pin |
| Контакт 97 | I/O — User I/O pin |
| Контакт 98 | I/O — User I/O pin |
| Контакт 99 | I/O — User I/O pin |
| Контакт 100 | I/O — User I/O pin |
| Контакт 101 | I/O — User I/O pin |
| Контакт 102 | VCC — 5.0 V supply |
| Контакт 103 | I/O — User I/O pin |
| Контакт 104 | I/O — User I/O pin |
| Контакт 105 | I/O — User I/O pin |
| Контакт 106 | I/O — User I/O pin |
| Контакт 107 | I/O — User I/O pin |
| Контакт 108 | I/O — User I/O pin |
| Контакт 109 | GND — Ground |
| Контакт 110 | I/O — User I/O pin |
| Контакт 111 | I/O — User I/O pin |
| Контакт 112 | I/O — User I/O pin |
| Контакт 113 | I/O — User I/O pin |
| Контакт 114 | I/O — User I/O pin |
| Контакт 115 | I/O — User I/O pin |
| Контакт 116 | I/O — User I/O pin |
| Контакт 117 | VCC — 5.0 V supply |
| Контакт 118 | I/O — User I/O pin |
| Контакт 119 | I/O — User I/O pin |
| Контакт 120 | I/O — User I/O pin |
| Контакт 121 | I/O — User I/O pin |
| Контакт 122 | I/O — User I/O pin |
| Контакт 123 | I/O — User I/O pin |
| Контакт 124 | GND — Ground |
| Контакт 125 | I/O — User I/O pin |
| Контакт 126 | I/O — User I/O pin |
| Контакт 127 | I/O — User I/O pin |
| Контакт 128 | I/O — User I/O pin |
| Контакт 129 | I/O — User I/O pin |
| Контакт 130 | I/O — User I/O pin |
| Контакт 131 | I/O — User I/O pin |
| Контакт 132 | VCC — 5.0 V supply |
| Контакт 133 | I/O — User I/O pin |
| Контакт 134 | I/O — User I/O pin |
| Контакт 135 | I/O — User I/O pin |
| Контакт 136 | I/O — User I/O pin |
| Контакт 137 | I/O — User I/O pin |
| Контакт 138 | I/O — User I/O pin |
| Контакт 139 | GND — Ground |
| Контакт 140 | I/O — User I/O pin |
| Контакт 141 | I/O — User I/O pin |
| Контакт 142 | I/O — User I/O pin |
| Контакт 143 | I/O — User I/O pin |
| Контакт 144 | I/O — User I/O pin |
| Контакт 145 | I/O — User I/O pin |
| Контакт 146 | I/O — User I/O pin |
| Контакт 147 | VCC — 5.0 V supply |
| Контакт 148 | I/O — User I/O pin |
| Контакт 149 | I/O — User I/O pin |
| Контакт 150 | I/O — User I/O pin |
| Контакт 151 | I/O — User I/O pin |
| Контакт 152 | I/O — User I/O pin |
| Контакт 153 | I/O — User I/O pin |
| Контакт 154 | GND — Ground |
| Контакт 155 | I/O — User I/O pin |
| Контакт 156 | I/O — User I/O pin |
| Контакт 157 | I/O — User I/O pin |
| Контакт 158 | I/O — User I/O pin |
| Контакт 159 | I/O — User I/O pin |
| Контакт 160 | I/O — User I/O pin |
| Контакт 161 | I/O — User I/O pin |
| Контакт 162 | VCC — 5.0 V supply |
| Контакт 163 | I/O — User I/O pin |
| Контакт 164 | I/O — User I/O pin |
| Контакт 165 | I/O — User I/O pin |
| Контакт 166 | I/O — User I/O pin |
| Контакт 167 | I/O — User I/O pin |
| Контакт 168 | I/O — User I/O pin |
| Контакт 169 | GND — Ground |
| Контакт 170 | I/O — User I/O pin |
| Контакт 171 | I/O — User I/O pin |
| Контакт 172 | I/O — User I/O pin |
| Контакт 173 | I/O — User I/O pin |
| Контакт 174 | I/O — User I/O pin |
| Контакт 175 | I/O — User I/O pin |
| Контакт 176 | I/O — User I/O pin |
| Контакт 177 | VCC — 5.0 V supply |
| Контакт 178 | I/O — User I/O pin |
| Контакт 179 | I/O — User I/O pin |
| Контакт 180 | I/O — User I/O pin |
| Контакт 181 | I/O — User I/O pin |
| Контакт 182 | I/O — User I/O pin |
| Контакт 183 | TDO — JTAG Test Data Out |
| Контакт 184 | I/O — User I/O pin |
| Контакт 185 | I/O — User I/O pin |
| Контакт 186 | I/O — User I/O pin |
| Контакт 187 | I/O — User I/O pin |
| Контакт 188 | I/O — User I/O pin |
| Контакт 189 | I/O — User I/O pin |
| Контакт 190 | I/O — User I/O pin |
| Контакт 191 | GND — Ground |
| Контакт 192 | I/O — User I/O pin |
| Контакт 193 | I/O — User I/O pin |
| Контакт 194 | I/O — User I/O pin |
| Контакт 195 | I/O — User I/O pin |
| Контакт 196 | I/O — User I/O pin |
| Контакт 197 | I/O — User I/O pin |
| Контакт 198 | I/O — User I/O pin |
| Контакт 199 | I/O — User I/O pin |
| Контакт 200 | I/O — User I/O pin |
| Контакт 201 | I/O — User I/O pin |
| Контакт 202 | I/O — User I/O pin |
| Контакт 203 | I/O — User I/O pin |
| Контакт 204 | I/O — User I/O pin |
| Контакт 205 | I/O — User I/O pin |
| Контакт 206 | I/O — User I/O pin |
| Контакт 207 | I/O — User I/O pin |
| Контакт 208 | I/O — User I/O pin |
Типичное применение
EPM9320RC208-20 подходит для 6 применениеs: 5 V Industrial Glue-Logic Consolidation, Legacy Microprocessor Address Decoding, Telecom Backplane Bus Interface Bridging, State-Machine Replacement in Test & Measurement, Peripheral Control Logic in Networking Equipment, Safety-Critical Power-On Control Logic.
5 V Industrial Glue-Logic Consolidation
The EPM9320RC208-20's 320 macrocells, 132 user I/O pins, and 5.0 V single-supply operation make it ideal for replacing 8 to 15 discrete 22V10 / GAL / PAL devices with a single instant-on non-volatile CPLD in 5 V industrial controllers. Its deterministic 20 ns tPD across all macrocell paths eliminates the timing-variation issues that plague SRAM-based FPGAs in asynchronous designs, and the IEEE 1149.1 JTAG interface allows board-level boundary-scan test of every I/O pin. Engineers place it between a 5 V microcontroller and legacy peripherals (parallel ADCs, LCD drivers, opto-isolated outputs) to consolidate address decoding, chip-select generation, and timing-strobe logic. The exposed-pad 208-RQFP package dissipates enough heat for the device's typical 1.5 W active power in a sealed industrial enclosure without an external heatsink.
Рекомендуется
Legacy Microprocessor Address Decoding
In 5 V Intel 8086 / 68000 / VME-bus designs the EPM9320RC208-20 replaces dozens of 74LS138 / 74LS139 decoder trees with a single programmable decoder that can map the full 1 MB (or 16 MB) address space into dozens of chip-select regions. Its 132 I/O pins handle wide address-and-control buses directly, and the 20 ns tPD provides two-level decode within a single 8 MHz bus cycle without wait-state insertion. The instant-on EEPROM configuration means decoded chip-selects are valid at the first rising edge of the system clock after power-up - critical for legacy CPUs that fetch the reset vector before any software runs. JTAG boundary-scan verifies every decoded output during manufacturing test, eliminating bed-of-nails fixtures.
Рекомендуется
Telecom Backplane Bus Interface Bridging
The EPM9320RC208-20's 132 I/O pins and 5 V tolerance allow it to bridge between legacy TTL buses (e.g., H.110 CT-bus, SCSA, parallel TDM) and modern FPGAs in telecom line cards. It performs level conditioning, parity generation/checking, and protocol conversion at the backplane edge, isolating the higher-density downstream FPGA from bus contention. The 20 ns tPD is sufficient for 50 MHz backplane operation when used as a pipeline-stage register, and the IEEE 1149.1 JTAG chain integrates seamlessly with the board's existing boundary-scan test infrastructure. Non-volatile EEPROM configuration means the bridge comes up correctly even after a brownout or hot-swap event, which is essential for NEBS-compliant telecom equipment.
Рекомендуется
State-Machine Replacement in Test & Measurement
Test-and-measurement instruments use the EPM9320RC208-20 to implement complex sequencing state machines - scan-chain controllers, multiplexer switching matrices, calibration sequencers - that would otherwise consume dozens of 74LS / 74HC flip-flops. Its 320 macrocells encode multi-state machines with 8 to 10 bits of state plus dozens of transition outputs, all running at deterministic 20 ns latency that keeps stimulus timing reproducible. The 132 I/O pins drive front-panel relays, ADC mux gates, and status LEDs directly without buffer logic. Because the design is stored in on-chip EEPROM, instruments boot into the correct test sequence even in factory-floor environments where power is cycled frequently.
Рекомендуется
Peripheral Control Logic in Networking Equipment
Routers, switches, and media gateways use the EPM9320RC208-20 to consolidate PHY interface glue logic - MDIO bus multiplexing, LED status driving, SFP module presence detect, and packet-classifier pre-processing. Its 5 V I/O compatibility matches the levels used by many legacy PHYs, and the 20 ns propagation delay easily handles the 25 MHz MDC clock. The 320 macrocells encode enough state to drive 24+ SFP cage presence/LED signals plus interrupt-aggregation logic in a single chip. JTAG boundary-scan over all 132 I/Os accelerates board bring-up by detecting solder bridges and open pins during in-circuit test, which is critical when each line card carries dozens of high-density connectors.
Рекомендуется
Safety-Critical Power-On Control Logic
The EPM9320RC208-20's instant-on non-volatile EEPROM behavior makes it ideal for power-on sequencing and watchdog logic in safety-critical systems (medical devices, industrial PLCs, railway signaling). Unlike SRAM FPGAs that require milliseconds of configuration time, this CPLD drives valid outputs within nanoseconds of VCC crossing 4.75 V, ensuring that reset vectors, watchdog strobes, and power-rail enables are present before any downstream host CPU or DSP boots. Its 320 macrocells encode dozens of independent sequencer channels, and the 132 I/O pins drive housekeeping signals directly. The deterministic 20 ns tPD simplifies worst-case timing analysis required by IEC 61508 SIL-2/3 functional-safety documentation.
Рекомендуется
Сводка рекомендуемых товаров
Справочные инженерные данные для EPM9320RC208-20 — сравнение, рекомендации по проектированию и информация о соответствии.
Руководство по выбору
Сравнение с аналогами
| Параметр | Этот товар | EPM9320RC208-15 | EPM9320RC208-15N | EPM9320RC208-10 | EPM9320ARC208-10 |
|---|---|---|---|---|---|
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Package | 208-RQFP (exposed pad) | 208-RQFP (exposed pad) - same | 208-RQFP (exposed pad) - same | 208-RQFP (exposed pad) - same | 208-RQFP (exposed pad) - same |
| Macrocells | 320 | 320 | 320 | 320 | 320 |
| Max I/O | 132 | 132 | 132 | 132 | 132 |
| Propagation Delay (tPD max) | 20 ns | 15 ns (faster) | 15 ns (faster) | 10 ns (faster) | 10 ns (faster) |
| Supply Voltage | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V |
| Programming Technology | EEPROM (ISP via JTAG) | EEPROM (ISP via JTAG) | EEPROM (ISP via JTAG) | EEPROM (ISP via JTAG) | EEPROM (ISP via JTAG) |
| Operating Temperature | 0 °C to 70 °C | 0 °C to 70 °C | 0 °C to 70 °C | 0 °C to 70 °C | 0 °C to 70 °C |
| Lifecycle Status | Obsolete | Obsolete (same family) | Obsolete (same family) | Obsolete (same family) | Obsolete (same family) |
Ключевые отличия
- Slowest speed grade in the EPM9320RC208 family, lowest secondary-market cost (против EPM9320RC208-15)
- 320-macrocell density vs lower-end MAX 7000S family members (против EPM7256SQC208-10)
- MAX 9000 EEPROM instant-on vs MAX II SRAM configuration delay (против EPM240T100C5N (MAX II))
Заметки по проектированию
Solder the exposed thermal pad on the underside of the 208-RQFP package to a PCB ground plane with at least 1 square inch (645 mm²) of copper area. The MAX 9000 device dissipates roughly 1.5 W at 100% macrocell utilization at 5 V, and without the thermal pad soldered junction temperature can exceed 100 °C even at room ambient. Estimate: at 1.5 W with 1 sq-in. copper pour, θJA ≈ 18 °C/W yields a 27 °C rise above 25 °C ambient (52 °C junction), well within the 70 °C commercial ceiling. For sealed industrial enclosures above 50 °C ambient, expand the copper area to 2-3 sq-in. or add forced-air cooling.
Decouple every VCC pin with a 0.1 µF ceramic capacitor placed within 3 mm (0.12 in.) of the supply pin and tie the GND return directly to the inner ground plane via a short via. Add one bulk 10 µF tantalum or aluminum-polymer capacitor near the corner of the package to handle simultaneous-switching-output (SSO) current transients from the 132 I/O pins. Place the JTAG TCK trace away from the I/O banks and add a 10 kΩ pull-up on TMS and TDI, plus a 10 kΩ pull-down on TRST to keep the boundary-scan state machine in known state during power-up.
Do not exceed 5.25 V on VCCINT even momentarily - the EEPROM programming circuits can latch-up above 6 V. Do not leave unused I/O pins floating; configure them in MAX+PLUS II / Quartus as outputs driving '0' or as inputs with internal pull-ups enabled, otherwise floating inputs draw 10-100 µA each and increase total quiescent current. Verify JTAG chain order in BSDL files when multiple MAX devices share one TCK/TMS bus - a reversed chain will pass boundary-scan tests but fail ISP programming. Finally, allow at least 50 ms after VCC stabilizes before initiating JTAG operations because the EEPROM charge pump requires settling time.
Информация о соответствии
EPM9320RC208-20 predates widespread RoHS conversion requirements; compliance depends on the specific date code and assembly variant. Standard Altera lead-finish parts carry SnPb solder, while lead-free variants (suffix 'N' such as EPM9320RC208-15N) are RoHS-compliant. Request specific compliance certificates from the supplier for each lot. Not AEC-Q100 qualified (industrial/consumer grade only).
