EPM9400RC240-20 - 400 MC, 20 ns MAX 9000 CPLD, 240-RQFP | Altera
MPN: EPM9400RC240-20 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $36.5 | $36.50 |
| 10 | $33.2 | $332.00 |
| 100 | $29.75 | $2,975.00 |
| 500 | $26.4 | $13,200.00 |
| 1,000 | $23.85 | $23,850.00 |
Drop-in alternatives for EPM9400RC240-20 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM9400RC240-15
β Drop-Inβ In Stock
$22.4 / Unit
View Datasheet βEPM9400RC240-20 Maximum Ratings & Electrical Characteristics
| Device Family | MAX 9000 |
| Macrocells | 400 |
| Pin-to-Pin Delay (tPD) | 20 ns |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V |
| Programmable Type | In System Programmable (EEPROM) |
| Programming Interface | IEEE Std. 1149.1 JTAG |
| Package | 240-RQFP (32x32 mm) with exposed pad |
| Supplier Device Package | 240-RQFP |
| Mounting Type | Surface Mount |
| Technology | CMOS, EEPROM-based |
| Architecture | MAX (Multiple Array MatriX) - third generation |
| Series | MAX 9000 |
EPM9400RC240-20 Pin Configuration
| Pin 1 | I/O β User I/O pin (MAX 9000 bank 1) |
| Pin 2 | I/O β User I/O pin |
| Pin 3 | I/O β User I/O pin |
| Pin 4 | I/O β User I/O pin |
| Pin 5 | GND β Ground |
| Pin 6 | I/O β User I/O pin |
| Pin 7 | I/O β User I/O pin |
| Pin 8 | I/O β User I/O pin |
| Pin 9 | I/O β User I/O pin |
| Pin 10 | I/O β User I/O pin |
| Pin 11 | VCC β 5 V supply |
| Pin 12 | I/O β User I/O pin |
| Pin 13 | I/O β User I/O pin |
| Pin 14 | I/O β User I/O pin |
| Pin 15 | I/O β User I/O pin |
| Pin 16 | I/O β User I/O pin |
| Pin 17 | GND β Ground |
| Pin 18 | I/O β User I/O pin |
| Pin 19 | I/O β User I/O pin |
| Pin 20 | I/O β User I/O pin |
| Pin 21 | I/O β User I/O pin |
| Pin 22 | I/O β User I/O pin |
| Pin 23 | VCC β 5 V supply |
| Pin 24 | I/O β User I/O pin |
| Pin 25 | I/O β User I/O pin |
| Pin 26 | I/O β User I/O pin |
| Pin 27 | I/O β User I/O pin |
| Pin 28 | I/O β User I/O pin |
| Pin 29 | GND β Ground |
| Pin 30 | I/O β User I/O pin |
| Pin 31 | I/O β User I/O pin |
| Pin 32 | I/O β User I/O pin |
| Pin 33 | I/O β User I/O pin |
| Pin 34 | I/O β User I/O pin |
| Pin 35 | VCC β 5 V supply |
| Pin 36 | I/O β User I/O pin |
| Pin 37 | I/O β User I/O pin |
| Pin 38 | I/O β User I/O pin |
| Pin 39 | I/O β User I/O pin |
| Pin 40 | I/O β User I/O pin |
| Pin 41 | GND β Ground |
| Pin 42 | I/O β User I/O pin |
| Pin 43 | I/O β User I/O pin |
| Pin 44 | I/O β User I/O pin |
| Pin 45 | I/O β User I/O pin |
| Pin 46 | I/O β User I/O pin |
| Pin 47 | VCC β 5 V supply |
| Pin 48 | I/O β User I/O pin |
| Pin 49 | I/O β User I/O pin |
| Pin 50 | I/O β User I/O pin |
| Pin 51 | I/O β User I/O pin |
| Pin 52 | I/O β User I/O pin |
| Pin 53 | GND β Ground |
| Pin 54 | I/O β User I/O pin |
| Pin 55 | I/O β User I/O pin |
| Pin 56 | I/O β User I/O pin |
| Pin 57 | I/O β User I/O pin |
| Pin 58 | I/O β User I/O pin |
| Pin 59 | VCC β 5 V supply |
| Pin 60 | I/O β User I/O pin |
| Pin 61 | I/O β User I/O pin |
| Pin 62 | I/O β User I/O pin |
| Pin 63 | I/O β User I/O pin |
| Pin 64 | I/O β User I/O pin |
| Pin 65 | GND β Ground |
| Pin 66 | I/O β User I/O pin |
| Pin 67 | I/O β User I/O pin |
| Pin 68 | I/O β User I/O pin |
| Pin 69 | I/O β User I/O pin |
| Pin 70 | I/O β User I/O pin |
| Pin 71 | VCC β 5 V supply |
| Pin 72 | I/O β User I/O pin |
| Pin 73 | I/O β User I/O pin |
| Pin 74 | I/O β User I/O pin |
| Pin 75 | I/O β User I/O pin |
| Pin 76 | I/O β User I/O pin |
| Pin 77 | GND β Ground |
| Pin 78 | I/O β User I/O pin |
| Pin 79 | I/O β User I/O pin |
| Pin 80 | I/O β User I/O pin |
| Pin 81 | I/O β User I/O pin |
| Pin 82 | I/O β User I/O pin |
| Pin 83 | VCC β 5 V supply |
| Pin 84 | I/O β User I/O pin |
| Pin 85 | I/O β User I/O pin |
| Pin 86 | I/O β User I/O pin |
| Pin 87 | I/O β User I/O pin |
| Pin 88 | I/O β User I/O pin |
| Pin 89 | GND β Ground |
| Pin 90 | I/O β User I/O pin |
| Pin 91 | I/O β User I/O pin |
| Pin 92 | I/O β User I/O pin |
| Pin 93 | I/O β User I/O pin |
| Pin 94 | I/O β User I/O pin |
| Pin 95 | VCC β 5 V supply |
| Pin 96 | I/O β User I/O pin |
| Pin 97 | I/O β User I/O pin |
| Pin 98 | I/O β User I/O pin |
| Pin 99 | I/O β User I/O pin |
| Pin 100 | I/O β User I/O pin |
| Pin 101 | GND β Ground |
| Pin 102 | I/O β User I/O pin |
| Pin 103 | I/O β User I/O pin |
| Pin 104 | I/O β User I/O pin |
| Pin 105 | I/O β User I/O pin |
| Pin 106 | I/O β User I/O pin |
| Pin 107 | VCC β 5 V supply |
| Pin 108 | I/O β User I/O pin |
| Pin 109 | I/O β User I/O pin |
| Pin 110 | I/O β User I/O pin |
| Pin 111 | I/O β User I/O pin |
| Pin 112 | I/O β User I/O pin |
| Pin 113 | GND β Ground |
| Pin 114 | I/O β User I/O pin |
| Pin 115 | I/O β User I/O pin |
| Pin 116 | I/O β User I/O pin |
| Pin 117 | I/O β User I/O pin |
| Pin 118 | I/O β User I/O pin |
| Pin 119 | VCC β 5 V supply |
| Pin 120 | I/O β User I/O pin |
| Pin 121 | I/O β User I/O pin |
| Pin 122 | I/O β User I/O pin |
| Pin 123 | I/O β User I/O pin |
| Pin 124 | I/O β User I/O pin |
| Pin 125 | GND β Ground |
| Pin 126 | I/O β User I/O pin |
| Pin 127 | I/O β User I/O pin |
| Pin 128 | I/O β User I/O pin |
| Pin 129 | I/O β User I/O pin |
| Pin 130 | I/O β User I/O pin |
| Pin 131 | VCC β 5 V supply |
| Pin 132 | I/O β User I/O pin |
| Pin 133 | I/O β User I/O pin |
| Pin 134 | I/O β User I/O pin |
| Pin 135 | I/O β User I/O pin |
| Pin 136 | I/O β User I/O pin |
| Pin 137 | GND β Ground |
| Pin 138 | I/O β User I/O pin |
| Pin 139 | I/O β User I/O pin |
| Pin 140 | I/O β User I/O pin |
| Pin 141 | I/O β User I/O pin |
| Pin 142 | I/O β User I/O pin |
| Pin 143 | VCC β 5 V supply |
| Pin 144 | I/O β User I/O pin |
| Pin 145 | I/O β User I/O pin |
| Pin 146 | I/O β User I/O pin |
| Pin 147 | I/O β User I/O pin |
| Pin 148 | I/O β User I/O pin |
| Pin 149 | GND β Ground |
| Pin 150 | I/O β User I/O pin |
| Pin 151 | I/O β User I/O pin |
| Pin 152 | I/O β User I/O pin |
| Pin 153 | I/O β User I/O pin |
| Pin 154 | I/O β User I/O pin |
| Pin 155 | VCC β 5 V supply |
| Pin 156 | I/O β User I/O pin |
| Pin 157 | I/O β User I/O pin |
| Pin 158 | I/O β User I/O pin |
| Pin 159 | I/O β User I/O pin |
| Pin 160 | I/O β User I/O pin |
| Pin 161 | GND β Ground |
| Pin 162 | I/O β User I/O pin |
| Pin 163 | I/O β User I/O pin |
| Pin 164 | I/O β User I/O pin |
| Pin 165 | I/O β User I/O pin |
| Pin 166 | I/O β User I/O pin |
| Pin 167 | VCC β 5 V supply |
| Pin 168 | I/O β User I/O pin |
| Pin 169 | I/O β User I/O pin |
| Pin 170 | I/O β User I/O pin |
| Pin 171 | I/O β User I/O pin |
| Pin 172 | I/O β User I/O pin |
| Pin 173 | GND β Ground |
| Pin 174 | I/O β User I/O pin |
| Pin 175 | I/O β User I/O pin |
| Pin 176 | I/O β User I/O pin |
| Pin 177 | I/O β User I/O pin |
| Pin 178 | I/O β User I/O pin |
| Pin 179 | VCC β 5 V supply |
| Pin 180 | I/O β User I/O pin |
| Pin 181 | I/O β User I/O pin |
| Pin 182 | I/O β User I/O pin |
| Pin 183 | I/O β User I/O pin |
| Pin 184 | I/O β User I/O pin |
| Pin 185 | GND β Ground |
| Pin 186 | I/O β User I/O pin |
| Pin 187 | I/O β User I/O pin |
| Pin 188 | I/O β User I/O pin |
| Pin 189 | I/O β User I/O pin |
| Pin 190 | I/O β User I/O pin |
| Pin 191 | VCC β 5 V supply |
| Pin 192 | I/O β User I/O pin |
| Pin 193 | I/O β User I/O pin |
| Pin 194 | I/O β User I/O pin |
| Pin 195 | I/O β User I/O pin |
| Pin 196 | I/O β User I/O pin |
| Pin 197 | GND β Ground |
| Pin 198 | I/O β User I/O pin |
| Pin 199 | I/O β User I/O pin |
| Pin 200 | I/O β User I/O pin |
| Pin 201 | I/O β User I/O pin |
| Pin 202 | I/O β User I/O pin |
| Pin 203 | VCC β 5 V supply |
| Pin 204 | I/O β User I/O pin |
| Pin 205 | I/O β User I/O pin |
| Pin 206 | I/O β User I/O pin |
| Pin 207 | I/O β User I/O pin |
| Pin 208 | I/O β User I/O pin |
| Pin 209 | GND β Ground |
| Pin 210 | I/O β User I/O pin |
| Pin 211 | I/O β User I/O pin |
| Pin 212 | I/O β User I/O pin |
| Pin 213 | I/O β User I/O pin |
| Pin 214 | I/O β User I/O pin |
| Pin 215 | VCC β 5 V supply |
| Pin 216 | I/O β User I/O pin |
| Pin 217 | I/O β User I/O pin |
| Pin 218 | I/O β User I/O pin |
| Pin 219 | I/O β User I/O pin |
| Pin 220 | I/O β User I/O pin |
| Pin 221 | GND β Ground |
| Pin 222 | I/O β User I/O pin |
| Pin 223 | I/O β User I/O pin |
| Pin 224 | I/O β User I/O pin |
| Pin 225 | I/O β User I/O pin |
| Pin 226 | I/O β User I/O pin |
| Pin 227 | VCC β 5 V supply |
| Pin 228 | I/O β User I/O pin |
| Pin 229 | I/O β User I/O pin |
| Pin 230 | I/O β User I/O pin |
| Pin 231 | I/O β User I/O pin |
| Pin 232 | I/O β User I/O pin |
| Pin 233 | GND β Ground (exposed thermal pad) |
| Pin 234 | TCK β JTAG test clock (dedicated) |
| Pin 235 | TMS β JTAG test mode select (dedicated) |
| Pin 236 | TDI β JTAG test data in (dedicated) |
| Pin 237 | TDO β JTAG test data out (dedicated) |
| Pin 238 | INPUT1 β Dedicated input pin 1 (DEV_CLRn/DEV_OE variant per design) |
| Pin 239 | INPUT2 β Dedicated input pin 2 (GCLK1 variant per design) |
| Pin 240 | INPUT3 β Dedicated input pin 3 (GCLK2 variant per design) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM9400RC240-20 is suitable for 6 applications: Address Decoding and Bus Interface Logic, Industrial Control and PLC Logic, Legacy 5 V System Upgrade Paths, Peripheral Glue Logic for Microcontrollers, JTAG Boundary-Scan Test Integration, Telecommunications Backplane Glue Logic.
Address Decoding and Bus Interface Logic
The EPM9400RC240-20's 400 macrocells and 240 I/O pins make it well suited for address-decoding and bus-interface glue logic in 5 V embedded systems, including ISA, PC/104, and custom 8/16/32-bit microprocessor buses. Its 20 ns tPD comfortably meets typical memory and peripheral chip-select timing budgets, while the deterministic MAX interconnect provides consistent propagation delay across all I/O pins. Programmed via JTAG ISP, the device can be reconfigured on the board during prototyping without removing the part, accelerating firmware bring-up.
Recommended
Industrial Control and PLC Logic
In industrial control boards and PLCs, the EPM9400RC240-20 provides deterministic non-volatile glue logic that retains configuration through power cycles without an external boot PROM. Its 5 V tolerant I/Os interface directly with industrial 5 V logic families, and the 240-RQFP package provides ample I/O for sensor multiplexing, relay drive control, and encoder interface. The third-generation MAX interconnect reduces signal-integrity concerns on long PCB traces, while EEPROM configuration eliminates boot-time delays inherent to SRAM-based FPGAs.
Recommended
Legacy 5 V System Upgrade Paths
The EPM9400RC240-20 is widely used in legacy 5 V system upgrades where newer 3.3 V CPLDs cannot interface directly with 5 V logic. Its 4.75 V to 5.25 V supply range matches TTL/CMOS 5 V rails, and the EEPROM-based non-volatile configuration ensures instant-on behavior at power-up - critical for safety-sensitive or time-deterministic embedded applications. Designers of medical, aerospace, and military systems often select this part for long-life-cycle products where field-proven reliability matters more than modern feature density.
Recommended
Peripheral Glue Logic for Microcontrollers
When interfacing microcontrollers to external peripherals (DRAM, FPGAs, ADCs, DACs), the EPM9400RC240-20 handles custom timing, bus-format conversion, and chip-select generation in a single non-volatile device. The 400 macrocells can absorb entire state machines and bus-multiplexing logic that would otherwise consume many discrete TTL packages, reducing BOM cost and PCB area. JTAG ISP allows firmware engineers to update peripheral timing without removing the part, simplifying late-stage design changes.
Recommended
JTAG Boundary-Scan Test Integration
The built-in IEEE Std. 1149.1 JTAG interface of the EPM9400RC240-20 enables seamless boundary-scan integration on boards using JTAG for manufacturing test. The part supports JTAG chain inclusion alongside other 1149.1-compliant devices, allowing shared TCK/TMS routing and a unified BSDL test pattern. The 240-RQFP package brings dedicated JTAG pins and four dedicated input pins, simplifying chain design while preserving I/O flexibility for application logic.
Recommended
Telecommunications Backplane Glue Logic
In telecom backplanes and access-network equipment, the EPM9400RC240-20 implements line-card interface logic, clock-distribution control, and alarm-handling state machines with predictable 20 ns timing. Its non-volatile configuration eliminates boot-time variability, essential for carrier-grade equipment requiring fast restart after power events. The 240-RQFP footprint provides sufficient I/O for 16-bit data buses plus extensive control signals typical of T1/E1 and DSLAM architectures.
Recommended
Recommended Products Summary
Engineering reference data for EPM9400RC240-20 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9400RC240-15 | EPM9400RC208-20 | EPM9320GC280-20 | EPM9320RI208-20 | EPM7256SRI208-10 |
|---|---|---|---|---|---|---|
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Package | 240-RQFP (32x32 mm) | 240-RQFP (32x32 mm) - same | 208-RQFP - different | 280-PGA - different | 208-RQFP - different | 208-RQFP - different |
| Macrocells | 400 | 400 (same) | 400 (same) | 320 (-20%) | 320 (-20%) | 256 (-36%) |
| Pin-to-Pin Delay (tPD) | 20 ns | 15 ns (-25%, faster) | 20 ns (same) | 20 ns (same) | 20 ns (same) | 10 ns (-50%, faster) |
| Supply Voltage | 4.75 V to 5.25 V | 4.75 V to 5.25 V (same) | 4.75 V to 5.25 V (same) | 4.75 V to 5.25 V (same) | 4.75 V to 5.25 V (same) | 4.75 V to 5.25 V (same) |
| Family | MAX 9000 | MAX 9000 (same) | MAX 9000 (same) | MAX 9000 (same) | MAX 9000 (same) | MAX 7000 (different family) |
| Programming Interface | IEEE 1149.1 JTAG ISP (EEPROM) | IEEE 1149.1 JTAG ISP (EEPROM) | IEEE 1149.1 JTAG ISP (EEPROM) | IEEE 1149.1 JTAG ISP (EEPROM) | IEEE 1149.1 JTAG ISP (EEPROM) | IEEE 1149.1 JTAG ISP (EEPROM) |
| Lifecycle Status | NRND | NRND | NRND | NRND | NRND | NRND |
Key Differentiators
- Same-package faster tPD drop-in option available (vs EPM9400RC240-15)
- Highest macrocell density in MAX 9000 family (vs EPM9320RI208-20)
- MAX 9000 architecture with third-generation MAX interconnect (vs EPM7256SRI208-10)
Design Notes
The EPM9400RC240-20 requires a single 5 V supply (4.75 V to 5.25 V). Per the Operating Requirements for Altera Devices Data Sheet, VCC must rise monotonically during power-up to ensure reliable ISP operation. Inputs may undershoot to -2.0 V or overshoot to 7.0 V only for periods shorter than 20 ns under no-load conditions. DC input levels must remain within -0.5 V on I/O pins and -0.3 V on the four dedicated input pins. Decoupling: place 0.1 uF ceramic capacitors close to every VCC/GND pair on the 240-RQFP package to suppress switching noise.
Route JTAG signals (TCK, TMS, TDI, TDO) as a clean daisy chain if multiple 1149.1 devices share the same JTAG bus. Keep JTAG traces short and isolated from switching signals; add 10 kohm pull-ups on TMS and TDI to prevent spurious test-mode entry. The exposed thermal pad on the 240-RQFP must be soldered to a ground plane for mechanical stability and thermal dissipation, even though the MAX 9000 family is CMOS-low-power.
Do not assume the EPM9400RC240-20 is still recommended for new designs - it is classified NRND by Altera/Intel. For new designs, evaluate MAX II or MAX V CPLDs, which offer lower power and modern features but require a different PCB footprint (not pin-compatible). Also, when migrating an existing design to the EPM9400RC240-15 (faster 15 ns tPD), verify the Quartus II/MAX+PLUS II timing simulation still meets all setup/hold requirements under worst-case conditions.
Compliance Information
RoHS and halogen-free status not directly stated in the verified web data; lead-free is typical for Altera/Intel 5 V MAX 9000 family. AEC-Q100 not applicable for commercial/industrial CPLD. Conflict-minerals compliance per Intel published CMRT.
