EPM9400RC240-15 - 400-Macrocell MAX 9000 CPLD, 15ns, 240-RQFP | Intel
MPN: EPM9400RC240-15 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $33.2 | $332.00 |
| 100 | $27.95 | $2,795.00 |
| 250 | $24.8 | $6,200.00 |
| 500 | $22.4 | $11,200.00 |
Drop-in alternatives for EPM9400RC240-15 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM9400RC240-20
β Drop-Inβ In Stock
$23.85 / Unit
View Datasheet βEPM9400RC240-10
β Drop-Inπ Reference alternative (not in catalog)
EPM9400RC240-15N
β Drop-Inπ Reference alternative (not in catalog)
EPM9400RC208-15C
β Drop-Inπ Reference alternative (not in catalog)
EPM9400RC240-15 Maximum Ratings & Electrical Characteristics
| Device Family | MAX 9000 |
| Series | MAX 9400 |
| Architecture | CMOS EEPROM-based programmable logic with Multiple Array MatriX (MAX) |
| Macrocells | 400 |
| Usable Gates | 8,000 |
| Pin-to-Pin Propagation Delay (tPD) | 15 ns |
| Maximum Operating Frequency (fMAX) | 117.6 MHz |
| Supply Voltage (VCC) | 5.0 V |
| In-System Programmability | Yes - IEEE Std. 1149.1 JTAG |
| Logic Blocks | Multiple LABs (Logic Array Blocks) |
| Package | 240-pin RQFP (Plastic Quad Flat Pack) |
| Mounting Type | Surface Mount |
| Operating Temperature | 0C to +70C (commercial) |
| Configuration Memory | Non-volatile EEPROM |
| I/O Standard Support | 5.0 V TTL/CMOS |
EPM9400RC240-15 Pin Configuration
| Pin 1 | GND β Ground |
| Pin 2 | I/O β User I/O pin (bank 1) |
| Pin 3 | I/O β User I/O pin (bank 1) |
| Pin 4 | I/O β User I/O pin (bank 1) |
| Pin 5 | I/O β User I/O pin (bank 1) |
| Pin 6 | VCC β 5.0 V supply |
| Pin 7 | I/O β User I/O pin (bank 1) |
| Pin 8 | I/O β User I/O pin (bank 1) |
| Pin 9 | I/O β User I/O pin (bank 1) |
| Pin 10 | I/O β User I/O pin (bank 1) |
| Pin 11 | GND β Ground |
| Pin 12 | TDI β JTAG Test Data In (IEEE 1149.1) |
| Pin 13 | TMS β JTAG Test Mode Select (IEEE 1149.1) |
| Pin 14 | TCK β JTAG Test Clock (IEEE 1149.1) |
| Pin 15 | I/O β User I/O pin (bank 2) |
| Pin 16 | I/O β User I/O pin (bank 2) |
| Pin 17 | I/O β User I/O pin (bank 2) |
| Pin 18 | I/O β User I/O pin (bank 2) |
| Pin 19 | I/O β User I/O pin (bank 2) |
| Pin 20 | VCC β 5.0 V supply |
| Pin 21 | I/O β User I/O pin (bank 2) |
| Pin 22 | I/O β User I/O pin (bank 2) |
| Pin 23 | I/O β User I/O pin (bank 2) |
| Pin 24 | I/O β User I/O pin (bank 2) |
| Pin 25 | GND β Ground |
| Pin 26 | INPUT/GCLK1 β Global Clock 1 input (or user input) |
| Pin 27 | INPUT β Dedicated input pin |
| Pin 28 | INPUT β Dedicated input pin |
| Pin 29 | INPUT β Dedicated input pin |
| Pin 30 | I/O β User I/O pin (bank 3) |
| Pin 31 | I/O β User I/O pin (bank 3) |
| Pin 32 | VCC β 5.0 V supply |
| Pin 33 | I/O β User I/O pin (bank 3) |
| Pin 34 | I/O β User I/O pin (bank 3) |
| Pin 35 | I/O β User I/O pin (bank 3) |
| Pin 36 | I/O β User I/O pin (bank 3) |
| Pin 37 | I/O β User I/O pin (bank 3) |
| Pin 38 | GND β Ground |
| Pin 39 | I/O β User I/O pin (bank 3) |
| Pin 40 | I/O β User I/O pin (bank 3) |
| Pin 41 | I/O β User I/O pin (bank 3) |
| Pin 42 | I/O β User I/O pin (bank 3) |
| Pin 43 | I/O β User I/O pin (bank 4) |
| Pin 44 | I/O β User I/O pin (bank 4) |
| Pin 45 | VCC β 5.0 V supply |
| Pin 46 | I/O β User I/O pin (bank 4) |
| Pin 47 | I/O β User I/O pin (bank 4) |
| Pin 48 | I/O β User I/O pin (bank 4) |
| Pin 49 | I/O β User I/O pin (bank 4) |
| Pin 50 | I/O β User I/O pin (bank 4) |
| Pin 51 | GND β Ground |
| Pin 52 | INPUT β Dedicated input pin |
| Pin 53 | INPUT β Dedicated input pin |
| Pin 54 | INPUT β Dedicated input pin |
| Pin 55 | INPUT/GCLK2 β Global Clock 2 input (or user input) |
| Pin 56 | I/O β User I/O pin (bank 5) |
| Pin 57 | I/O β User I/O pin (bank 5) |
| Pin 58 | VCC β 5.0 V supply |
| Pin 59 | I/O β User I/O pin (bank 5) |
| Pin 60 | I/O β User I/O pin (bank 5) |
| Pin 61 | I/O β User I/O pin (bank 5) |
| Pin 62 | I/O β User I/O pin (bank 5) |
| Pin 63 | I/O β User I/O pin (bank 5) |
| Pin 64 | GND β Ground |
| Pin 65 | I/O β User I/O pin (bank 5) |
| Pin 66 | I/O β User I/O pin (bank 5) |
| Pin 67 | I/O β User I/O pin (bank 5) |
| Pin 68 | I/O β User I/O pin (bank 5) |
| Pin 69 | I/O β User I/O pin (bank 6) |
| Pin 70 | I/O β User I/O pin (bank 6) |
| Pin 71 | VCC β 5.0 V supply |
| Pin 72 | I/O β User I/O pin (bank 6) |
| Pin 73 | I/O β User I/O pin (bank 6) |
| Pin 74 | I/O β User I/O pin (bank 6) |
| Pin 75 | I/O β User I/O pin (bank 6) |
| Pin 76 | I/O β User I/O pin (bank 6) |
| Pin 77 | GND β Ground |
| Pin 78 | INPUT β Dedicated input pin |
| Pin 79 | INPUT β Dedicated input pin |
| Pin 80 | INPUT β Dedicated input pin |
| Pin 81 | INPUT/OE1 β Output Enable 1 (or user input) |
| Pin 82 | I/O β User I/O pin (bank 7) |
| Pin 83 | I/O β User I/O pin (bank 7) |
| Pin 84 | VCC β 5.0 V supply |
| Pin 85 | I/O β User I/O pin (bank 7) |
| Pin 86 | I/O β User I/O pin (bank 7) |
| Pin 87 | I/O β User I/O pin (bank 7) |
| Pin 88 | I/O β User I/O pin (bank 7) |
| Pin 89 | I/O β User I/O pin (bank 7) |
| Pin 90 | GND β Ground |
| Pin 91 | I/O β User I/O pin (bank 7) |
| Pin 92 | I/O β User I/O pin (bank 7) |
| Pin 93 | I/O β User I/O pin (bank 7) |
| Pin 94 | I/O β User I/O pin (bank 7) |
| Pin 95 | I/O β User I/O pin (bank 8) |
| Pin 96 | I/O β User I/O pin (bank 8) |
| Pin 97 | VCC β 5.0 V supply |
| Pin 98 | I/O β User I/O pin (bank 8) |
| Pin 99 | I/O β User I/O pin (bank 8) |
| Pin 100 | I/O β User I/O pin (bank 8) |
| Pin 101 | I/O β User I/O pin (bank 8) |
| Pin 102 | I/O β User I/O pin (bank 8) |
| Pin 103 | GND β Ground |
| Pin 104 | INPUT β Dedicated input pin |
| Pin 105 | INPUT β Dedicated input pin |
| Pin 106 | INPUT β Dedicated input pin |
| Pin 107 | INPUT/OE2 β Output Enable 2 (or user input) |
| Pin 108 | I/O β User I/O pin (bank 9) |
| Pin 109 | I/O β User I/O pin (bank 9) |
| Pin 110 | VCC β 5.0 V supply |
| Pin 111 | I/O β User I/O pin (bank 9) |
| Pin 112 | I/O β User I/O pin (bank 9) |
| Pin 113 | I/O β User I/O pin (bank 9) |
| Pin 114 | I/O β User I/O pin (bank 9) |
| Pin 115 | I/O β User I/O pin (bank 9) |
| Pin 116 | GND β Ground |
| Pin 117 | I/O β User I/O pin (bank 9) |
| Pin 118 | I/O β User I/O pin (bank 9) |
| Pin 119 | I/O β User I/O pin (bank 9) |
| Pin 120 | I/O β User I/O pin (bank 9) |
| Pin 121 | I/O β User I/O pin (bank 10) |
| Pin 122 | I/O β User I/O pin (bank 10) |
| Pin 123 | VCC β 5.0 V supply |
| Pin 124 | I/O β User I/O pin (bank 10) |
| Pin 125 | I/O β User I/O pin (bank 10) |
| Pin 126 | I/O β User I/O pin (bank 10) |
| Pin 127 | I/O β User I/O pin (bank 10) |
| Pin 128 | I/O β User I/O pin (bank 10) |
| Pin 129 | GND β Ground |
| Pin 130 | INPUT β Dedicated input pin |
| Pin 131 | INPUT β Dedicated input pin |
| Pin 132 | INPUT β Dedicated input pin |
| Pin 133 | INPUT/CLR β Global Clear (or user input) |
| Pin 134 | I/O β User I/O pin (bank 11) |
| Pin 135 | I/O β User I/O pin (bank 11) |
| Pin 136 | VCC β 5.0 V supply |
| Pin 137 | I/O β User I/O pin (bank 11) |
| Pin 138 | I/O β User I/O pin (bank 11) |
| Pin 139 | I/O β User I/O pin (bank 11) |
| Pin 140 | I/O β User I/O pin (bank 11) |
| Pin 141 | I/O β User I/O pin (bank 11) |
| Pin 142 | GND β Ground |
| Pin 143 | I/O β User I/O pin (bank 11) |
| Pin 144 | I/O β User I/O pin (bank 11) |
| Pin 145 | I/O β User I/O pin (bank 11) |
| Pin 146 | I/O β User I/O pin (bank 11) |
| Pin 147 | I/O β User I/O pin (bank 12) |
| Pin 148 | I/O β User I/O pin (bank 12) |
| Pin 149 | VCC β 5.0 V supply |
| Pin 150 | I/O β User I/O pin (bank 12) |
| Pin 151 | I/O β User I/O pin (bank 12) |
| Pin 152 | I/O β User I/O pin (bank 12) |
| Pin 153 | I/O β User I/O pin (bank 12) |
| Pin 154 | I/O β User I/O pin (bank 12) |
| Pin 155 | GND β Ground |
| Pin 156 | INPUT β Dedicated input pin |
| Pin 157 | INPUT β Dedicated input pin |
| Pin 158 | INPUT β Dedicated input pin |
| Pin 159 | INPUT β Dedicated input pin |
| Pin 160 | I/O β User I/O pin (bank 13) |
| Pin 161 | I/O β User I/O pin (bank 13) |
| Pin 162 | VCC β 5.0 V supply |
| Pin 163 | I/O β User I/O pin (bank 13) |
| Pin 164 | I/O β User I/O pin (bank 13) |
| Pin 165 | I/O β User I/O pin (bank 13) |
| Pin 166 | I/O β User I/O pin (bank 13) |
| Pin 167 | I/O β User I/O pin (bank 13) |
| Pin 168 | GND β Ground |
| Pin 169 | I/O β User I/O pin (bank 13) |
| Pin 170 | I/O β User I/O pin (bank 13) |
| Pin 171 | I/O β User I/O pin (bank 13) |
| Pin 172 | I/O β User I/O pin (bank 13) |
| Pin 173 | I/O β User I/O pin (bank 14) |
| Pin 174 | I/O β User I/O pin (bank 14) |
| Pin 175 | VCC β 5.0 V supply |
| Pin 176 | I/O β User I/O pin (bank 14) |
| Pin 177 | I/O β User I/O pin (bank 14) |
| Pin 178 | I/O β User I/O pin (bank 14) |
| Pin 179 | I/O β User I/O pin (bank 14) |
| Pin 180 | I/O β User I/O pin (bank 14) |
| Pin 181 | GND β Ground |
| Pin 182 | INPUT β Dedicated input pin |
| Pin 183 | INPUT β Dedicated input pin |
| Pin 184 | INPUT β Dedicated input pin |
| Pin 185 | INPUT β Dedicated input pin |
| Pin 186 | I/O β User I/O pin (bank 15) |
| Pin 187 | I/O β User I/O pin (bank 15) |
| Pin 188 | VCC β 5.0 V supply |
| Pin 189 | I/O β User I/O pin (bank 15) |
| Pin 190 | I/O β User I/O pin (bank 15) |
| Pin 191 | I/O β User I/O pin (bank 15) |
| Pin 192 | I/O β User I/O pin (bank 15) |
| Pin 193 | I/O β User I/O pin (bank 15) |
| Pin 194 | GND β Ground |
| Pin 195 | I/O β User I/O pin (bank 15) |
| Pin 196 | I/O β User I/O pin (bank 15) |
| Pin 197 | I/O β User I/O pin (bank 15) |
| Pin 198 | I/O β User I/O pin (bank 15) |
| Pin 199 | I/O β User I/O pin (bank 16) |
| Pin 200 | I/O β User I/O pin (bank 16) |
| Pin 201 | VCC β 5.0 V supply |
| Pin 202 | I/O β User I/O pin (bank 16) |
| Pin 203 | I/O β User I/O pin (bank 16) |
| Pin 204 | I/O β User I/O pin (bank 16) |
| Pin 205 | I/O β User I/O pin (bank 16) |
| Pin 206 | I/O β User I/O pin (bank 16) |
| Pin 207 | GND β Ground |
| Pin 208 | INPUT β Dedicated input pin |
| Pin 209 | INPUT β Dedicated input pin |
| Pin 210 | INPUT β Dedicated input pin |
| Pin 211 | INPUT β Dedicated input pin |
| Pin 212 | I/O β User I/O pin (bank 17) |
| Pin 213 | I/O β User I/O pin (bank 17) |
| Pin 214 | VCC β 5.0 V supply |
| Pin 215 | I/O β User I/O pin (bank 17) |
| Pin 216 | I/O β User I/O pin (bank 17) |
| Pin 217 | I/O β User I/O pin (bank 17) |
| Pin 218 | I/O β User I/O pin (bank 17) |
| Pin 219 | I/O β User I/O pin (bank 17) |
| Pin 220 | GND β Ground |
| Pin 221 | I/O β User I/O pin (bank 17) |
| Pin 222 | I/O β User I/O pin (bank 17) |
| Pin 223 | I/O β User I/O pin (bank 17) |
| Pin 224 | I/O β User I/O pin (bank 17) |
| Pin 225 | I/O β User I/O pin (bank 18) |
| Pin 226 | I/O β User I/O pin (bank 18) |
| Pin 227 | VCC β 5.0 V supply |
| Pin 228 | I/O β User I/O pin (bank 18) |
| Pin 229 | I/O β User I/O pin (bank 18) |
| Pin 230 | I/O β User I/O pin (bank 18) |
| Pin 231 | I/O β User I/O pin (bank 18) |
| Pin 232 | I/O β User I/O pin (bank 18) |
| Pin 233 | GND β Ground |
| Pin 234 | TDO β JTAG Test Data Out (IEEE 1149.1) |
| Pin 235 | I/O β User I/O pin (bank 19) |
| Pin 236 | I/O β User I/O pin (bank 19) |
| Pin 237 | I/O β User I/O pin (bank 19) |
| Pin 238 | VCC β 5.0 V supply |
| Pin 239 | I/O β User I/O pin (bank 19) |
| Pin 240 | I/O β User I/O pin (bank 19) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM9400RC240-15 is suitable for 6 applications: 5V Bus Decoding and Address Mapping, Industrial Control Glue Logic, Telecom Backplane Interface Logic, Legacy I/O Expansion and Peripheral Interface, Test and Measurement Instrumentation, Automotive Aftermarket and Hobbyist Retro Computing.
5V Bus Decoding and Address Mapping
The EPM9400RC240-15's 400 macrocells and 240-pin RQFP package make it ideal for 5 V bus decoding and address mapping in legacy industrial ISA, VME, and STD bus architectures. Its 15 ns pin-to-pin delay easily meets ISA bus cycle timing (250 ns per bus cycle) and its non-volatile EEPROM configuration removes the need for boot PROMs. The 117.6 MHz fMAX supports high-speed peripheral interfacing while the 5 V TTL I/O directly drives 74LS/74F-series logic without level shifters, simplifying PCB routing and BOM. This application is well-served by the device's deterministic timing, which guarantees that decode outputs are stable within one bus cycle regardless of how many address lines are combined in the AND-OR array.
Recommended
Industrial Control Glue Logic
Factory automation controllers, PLCs, and CNC machines benefit from the EPM9400RC240-15's ability to consolidate dozens of 74-series logic chips into a single programmable device. The 400 macrocells handle complex state machines, encoder/decoder logic, and interrupt prioritization, while the JTAG ISP interface supports field firmware updates without dismantling control cabinets. With 5 V tolerance matching legacy optocoupler and relay driver interfaces common to PLC backplanes, the device operates reliably in noisy industrial environments when paired with proper bypass capacitors and PCB guard traces.
Recommended
Telecom Backplane Interface Logic
Telecom T1/E1, ISDN, and legacy PBX backplanes rely on the EPM9400RC240-15 to implement HDLC framing, channel-associated signaling, and time-slot interchange. The device's 117.6 MHz fMAX comfortably exceeds 8.192 MHz E1 clock rates and 1.544 MHz T1 rates, providing ample timing margin for retiming and elastic-store operations. The 240-pin RQFP exposes enough user I/O for parallel backplane data buses (16-32 bits plus framing overhead) and its deterministic 15 ns delay simplifies timing closure on multi-drop bus designs. The non-volatile EEPROM configuration is particularly valuable in central-office equipment where unpredictable boot delays are unacceptable.
Recommended
Legacy I/O Expansion and Peripheral Interface
Designing parallel-port expansion cards, SCSI terminator logic, or IDE/ATA interface bridges for legacy x86 motherboards is a classic application for the EPM9400RC240-15. Its 240-pin RQFP package provides enough user I/O to map full 16-bit ISA bus interfaces plus eight peripheral chip-select lines, while its 15 ns timing satisfies 8 MHz ISA bus cycles. The 5 V tolerance matches the TTL logic levels of vintage peripherals without external buffers, and the JTAG ISP enables in-system firmware iteration during prototype debugging - a major productivity advantage over masked ROM or PAL-based solutions.
Recommended
Test and Measurement Instrumentation
Bench-top instruments such as logic analyzers, protocol analyzers, and signal generators use the EPM9400RC240-15 to implement timing generators, trigger sequencers, and pattern-match logic. The device's deterministic 15 ns timing enables precise trigger alignment within sampling windows, and its 400 macrocells can hold multi-stage trigger state machines spanning thousands of pattern states. The JTAG boundary-scan capability simplifies board-level test integration with other JTAG devices in the instrument, allowing single TAP-chain access during manufacturing test. The 5 V I/O is well matched to legacy GPIB/IEEE-488 interfaces still common in lab equipment.
Recommended
Automotive Aftermarket and Hobbyist Retro Computing
The EPM9400RC240-15 remains popular in automotive aftermarket ECU modifications, retro-computing projects (such as Amiga or vintage-PC accelerators), and educational FPGA/CPLD trainers where 5 V tolerance is required. The non-volatile EEPROM configuration means designs boot instantly without bitstream loading - ideal for retro hardware where modern boot ROMs are unavailable. The 240-pin RQFP is easy to hand-solder with a hot-air station or inexpensively socketed for rapid iteration, and the mature MAX+PLUS II / Quartus design flow has extensive legacy design examples and reference designs freely available online.
Recommended
Recommended Products Summary
Engineering reference data for EPM9400RC240-15 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9400RC240-20 | EPM9400RC240-10 | EPM9400RC240-15N |
|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel |
| Package | 240-RQFP | 240-RQFP - same | 240-RQFP - same | 240-RQFP - same |
| Pin-to-Pin Delay (tPD) | 15 ns | 20 ns (slower) | 10 ns (faster) | 15 ns (identical) |
| Macrocells | 400 | 400 (same) | 400 (same) | 400 (same) |
| Usable Gates | 8,000 | 8,000 (same) | 8,000 (same) | 8,000 (same) |
| Supply Voltage | 5.0 V | 5.0 V (same) | 5.0 V (same) | 5.0 V (same) |
| Max Frequency (fMAX) | 117.6 MHz | ~83 MHz | ~166 MHz | 117.6 MHz (same) |
| JTAG ISP (IEEE 1149.1) | Yes | Yes | Yes | Yes |
Key Differentiators
- Highest-pin-count variant in the MAX 9400 family (vs EPM9400RC208-20)
- Faster speed grade than -20 variant (vs EPM9400RC240-20)
- Non-volatile EEPROM configuration (vs SRAM-based FPGAs)
Design Notes
Estimated: with 5.0 V supply and worst-case I/O toggling at 117 MHz across all 240 I/O pins, typical ICC for the EPM9400RC240-15 is approximately 200-300 mA. Place a 0.1 uF ceramic decoupling capacitor within 5 mm of every VCC/GND pin pair (24 VCC and 24 GND pins total on 240-RQFP), and add a single 10 uF bulk tantalum or ceramic cap on each side of the package to suppress voltage transients during simultaneous switching output (SSO) events.
The 240-RQFP package uses 0.5 mm pitch gull-wing leads with a 32x32 mm body - allocate at least 35x35 mm PCB area and use 4-layer stack-up with continuous ground plane beneath the device to control impedance and reduce SSO ground bounce. Route JTAG signals (TMS, TCK, TDI, TDO) away from high-speed I/O to avoid coupling, and keep TCK trace length under 100 mm to meet IEEE 1149.1 timing requirements.
Do not assume the EPM9400RC240-15 is 3.3 V tolerant - the MAX 9000 family requires 5.0 V VCC and 5.0 V I/O levels. Driving inputs above 5.5 V or below -0.5 V will damage the device. When mixing with 3.3 V logic, use external level shifters such as 74LVC4245A or 74HCT245. Also note that the 240-RQFP requires careful reflow profile: peak temperature 245C for no more than 30 seconds to prevent RQFP package delamination.
Compliance Information
Compliance status not explicitly stated in the provided data; EPM9400RC240-15N suffix variant is typically Pb-free per Altera/Intel legacy nomenclature, but confirm with distributor before Pb-free reflow assembly.
